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Verilog-AMS to JSON Automatic Device Model Synthesizer
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Frandy/adms-1
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Parts of this project are a derived work of ADMS. Files in the admsJSON directory are under the GNU GPL Version 2.0. Other files may be subject to other license terms. Please look at the individual files in the project directories to determine their copyright and license terms. Copyright (C) 2015--2016 Luther T. Cat Original code copyright the original authors. Please see the INSTALL file for build instructions.
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Verilog-AMS to JSON Automatic Device Model Synthesizer
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- Yacc 49.4%
- C 20.5%
- C++ 17.1%
- Perl 7.5%
- Lex 2.7%
- Python 2.1%
- Other 0.7%