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miguelangelo78miguelangelo78
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Assigned Microcode controls to their respective assignment locations
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-108
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3 files changed

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‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/top.qws‎

1.94 KB
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‎rtl/fisc_core/fisc_core.sv‎

Lines changed: 55 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -14,16 +14,16 @@ module FISC_Core(
1414
output reg ioack_n, /* 0: CPU acknowledges IO request. 1: CPU is either serving an IRQ or is simply executing instructions in normal mode */
1515
output reg wr_a, /* 0: CPU writes to memory. 1: CPU is currently executing an instruction (channel a) */
1616
output reg rd_a, /* 0: CPU reads from memory. 1: CPU is currently executing an instruction (channel a) */
17-
output reg wr_b, /* 0: CPU writes to memory. 1: CPU is currently executing an instruction (channel b) */
18-
output reg rd_b, /* 0: CPU reads from memory. 1: CPU is currently executing an instruction (channel b) */
17+
output wr_b, /* 0: CPU writes to memory. 1: CPU is currently executing an instruction (channel b) */
18+
output rd_b, /* 0: CPU reads from memory. 1: CPU is currently executing an instruction (channel b) */
1919

2020
input [`FISC_INTEGER_SZ-1:0] din_bus_a, /* Data Input Bus (channel a) */
2121
output reg [`FISC_INTEGER_SZ-1:0] dout_bus_a, /* Data Output Bus (channel a) */
2222
output reg [`FISC_ADDRESS_BOOT_SZ-1:0] addr_bus_a, /* Address Bus (channel a) */
2323

2424
input [`FISC_INTEGER_SZ-1:0] din_bus_b, /* Data Input Bus (channel b) */
25-
output reg [`FISC_INTEGER_SZ-1:0] dout_bus_b, /* Data Output Bus (channel b) */
26-
output reg [`FISC_ADDRESS_BOOT_SZ-1:0] addr_bus_b, /* Address Bus (channel b) */
25+
output [`FISC_INTEGER_SZ-1:0] dout_bus_b, /* Data Output Bus (channel b) */
26+
output [`FISC_ADDRESS_BOOT_SZ-1:0] addr_bus_b, /* Address Bus (channel b) */
2727

2828
/* Debug wires */
2929
output dbg_init,
@@ -98,58 +98,68 @@ module FISC_Core(
9898
.dbg3(microcode_dbg3),
9999
.dbg4(microcode_dbg4)
100100
);
101-
101+
102+
/* Microcode control assignments */
103+
wire mcu_first_op_src = microcode_ctrl[23];
104+
wire mcu_reg_wr = microcode_ctrl[22];
105+
wire [3:0] mcu_reg_special_wr = microcode_ctrl[21:18];
106+
wire [3:0] mcu_reg_special_rd = microcode_ctrl[17:14];
107+
wire [1:0] mcu_reg_din_src = microcode_ctrl[13:12];
108+
wire [1:0] mcu_alu_src = microcode_ctrl[11:10];
109+
wire [3:0] mcu_alu_f = microcode_ctrl[9:6];
110+
wire mcu_mem_wr_b = microcode_ctrl[5];
111+
wire mcu_mem_rd_b = microcode_ctrl[4];
112+
wire mcu_branch = microcode_ctrl[3];
113+
wire mcu_pc_rel = microcode_ctrl[2];
114+
wire mcu_set_flags = microcode_ctrl[1];
115+
102116
/* Registers instantiation and wires */
103-
reg [5:0] rd_reg;
117+
reg [5:0] rd_reg1;
104118
reg [5:0] wr_reg;
105-
reg wr_fromreg;
106-
reg wr_fromimm;
107-
reg [`FISC_INTEGER_SZ-1:0] din_reg;
108-
wire [`FISC_INTEGER_SZ-1:0] dout_reg;
109-
119+
reg reg_wr;
120+
reg [`FISC_INTEGER_SZ-1:0] din;
121+
wire [`FISC_INTEGER_SZ-1:0] dout1;
122+
wire [`FISC_INTEGER_SZ-1:0] dout2;
123+
110124
Registers registers(
111125
.clk(clk),
112-
.rd_reg(rd_reg),
113-
.wr_reg(wr_reg),
114-
.wr_fromreg(wr_fromreg),
115-
.wr_fromimm(wr_fromimm),
116-
.din_reg(din_reg),
117-
.dout_reg(dout_reg)
126+
.rd_reg1(microcode_sos ? rd_reg1 : (mcu_reg_special_rd > 0 ? mcu_reg_special_rd + 31 : (mcu_first_op_src ? instruction[20:16] : instruction[9:5]))),
127+
.rd_reg2(microcode_sos ? rd_reg2 : (mcu_mem_wr_b ? instruction[4:0] : (mcu_first_op_src ? instruction[9:5] : instruction[20:16]))),
128+
.wr_reg(microcode_sos ? wr_reg : (mcu_reg_special_wr > 0 ? mcu_reg_special_wr + 31 : instruction[4:0])),
129+
.wr(microcode_sos ? reg_wr : mcu_reg_wr),
130+
.din(microcode_sos ? din : (mcu_reg_din_src == 1 ? alu_y : (mcu_reg_din_src == 2 ? din_bus_b : 'hX))),
131+
.dout1(dout1),
132+
.dout2(dout2),
133+
.set_flags(mcu_set_flags),
134+
.flag_negative(alu_flag_negative),
135+
.flag_zero(alu_flag_zero),
136+
.flag_overflow(alu_flag_overflow),
137+
.flag_carry(alu_flag_carry)
118138
);
119139

120-
task write_register(input [5:0] regno, input [`FISC_INTEGER_SZ-1:0] din);
140+
task write_register(input [5:0] regno, input [`FISC_INTEGER_SZ-1:0] din_register);
121141
/* Write immediate value into register */
122142
wr_reg <= regno;
123-
din_reg <= din;
124-
wr_fromimm <= 1;
125-
endtask
126-
127-
task copy_register(input [5:0] regno_src, input [5:0] regno_dst);
128-
/* Write a register's value into another register */
129-
wr_reg <= regno_dst;
130-
rd_reg <= regno_src;
131-
wr_fromreg <= 1;
143+
din <= din_register;
144+
reg_wr <= 1;
132145
endtask
133146

134147
function [`FISC_INTEGER_SZ-1:0] read_register(input [5:0] regno);
135-
rd_reg = regno;
136-
return dout_reg;
148+
rd_reg1 = regno;
149+
return dout1;
137150
endfunction
138151

139152
/* ALU instantiation and wires */
140-
wire [`FISC_INTEGER_SZ-1:0] alu_opA;
141-
wire [`FISC_INTEGER_SZ-1:0] alu_opB;
142-
wire [`ALU_F_SZ-1:0] alu_f;
143153
wire [`FISC_INTEGER_SZ-1:0] alu_y;
144154
wire alu_flag_negative;
145155
wire alu_flag_zero;
146156
wire alu_flag_overflow;
147157
wire alu_flag_carry;
148158

149159
ALU alu(
150-
.opA(alu_opA),
151-
.opB(alu_opB),
152-
.f(alu_f),
160+
.opA(dout1),
161+
.opB(mcu_alu_src == 0 ? instruction[21:10] : (mcu_alu_src == 1 ? dout2 : (mcu_alu_src == 2 ? din_bus_a : 'hX))),
162+
.f(mcu_alu_f),
153163
.y(alu_y),
154164
.flag_negative(alu_flag_negative),
155165
.flag_zero(alu_flag_zero),
@@ -158,43 +168,28 @@ module FISC_Core(
158168
);
159169

160170
/* Main memory controls */
161-
task write_memory(logic channel, input [`FISC_ADDRESS_BOOT_SZ-1:0] address, input [`FISC_INTEGER_SZ-1:0] din);
162-
if(!channel) begin
163-
addr_bus_a <= address;
164-
dout_bus_a <= din;
165-
wr_a <= 1;
166-
end else begin
167-
addr_bus_b <= address;
168-
dout_bus_b <= din;
169-
wr_b <= 1;
170-
end
171-
endtask
171+
assign dout_bus_b = dout2;
172+
assign addr_bus_b = alu_y[10:0];
173+
assign wr_b = mcu_mem_wr_b;
174+
assign rd_b = mcu_mem_rd_b;
172175

173-
task enable_read_memory(logic channel, input [`FISC_ADDRESS_BOOT_SZ-1:0] address);
174-
if(!channel) begin
176+
task enable_read_memory(input [`FISC_ADDRESS_BOOT_SZ-1:0] address);
175177
addr_bus_a <= address;
176178
rd_a <= 1;
177-
end else begin
178-
addr_bus_b <= address;
179-
rd_b <= 1;
180-
end
181179
endtask
182180

183-
function [`FISC_INTEGER_SZ-1:0] read_memory(logic channel);
184-
return !channel ? din_bus_a : din_bus_b;
181+
function [`FISC_INTEGER_SZ-1:0] read_memory;
182+
return din_bus_a;
185183
endfunction
186184

187185
task reset_control_wires;
188186
/* Memory controls */
189187
wr_a = 0;
190-
wr_b = 0;
191188
rd_a = 0;
192-
rd_b = 0;
193189

194190
/* Register controls */
195191
wr_reg = 0;
196-
wr_fromimm = 0;
197-
wr_fromreg = 0;
192+
reg_wr = 0;
198193

199194
/* Debug UART */
200195
debug_uart_stop();
@@ -230,7 +225,7 @@ module FISC_Core(
230225
logic [`FISC_INTEGER_SZ-1:0] current_pc = read_register(32);
231226

232227
/* Fetch memory block by first enabling read and setting the address */
233-
enable_read_memory(0, !current_pc ? current_pc : current_pc / 8);
228+
enable_read_memory(!current_pc ? current_pc : current_pc / 8);
234229

235230
cpu_state <= ST_FETCH2_INSTRUCTION;
236231
endtask
@@ -240,7 +235,7 @@ module FISC_Core(
240235
instruction from the local memory block */
241236

242237
/* Now we can latch the memory block */
243-
memory_block = read_memory(0);
238+
memory_block = read_memory();
244239

245240
/* Grab instruction from fetched memory block */
246241
if(fetch_word_tophalf == 0) begin

‎rtl/fisc_core/registers.sv‎

Lines changed: 55 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -2,12 +2,20 @@
22

33
module Registers(
44
input clk,
5-
input [5:0] rd_reg,
5+
input [5:0] rd_reg1, /* Read channel 1 */
6+
input [5:0] rd_reg2, /* Read channel 2 */
67
input [5:0] wr_reg,
7-
input wr_fromreg, /* 1: regfile[wr_reg] = regfile[rd_reg] | 0: dout_reg = regfile[rd_reg] */
8-
input wr_fromimm, /* 1: regfile[wr_reg = din_reg | 0: dout_reg = regfile[rd_reg] */
9-
input [`FISC_INTEGER_SZ-1:0] din_reg,
10-
output [`FISC_INTEGER_SZ-1:0] dout_reg
8+
input wr, /* 1: regfile[wr_reg] = din | 0: - */
9+
input [`FISC_INTEGER_SZ-1:0] din,
10+
output [`FISC_INTEGER_SZ-1:0] dout1, /* Data output from channel 1 */
11+
output [`FISC_INTEGER_SZ-1:0] dout2, /* Data output from channel 2 */
12+
13+
/* Flags */
14+
input set_flags,
15+
input flag_negative,
16+
input flag_zero,
17+
input flag_overflow,
18+
input flag_carry
1119
);
1220

1321
/* Registers supported */
@@ -16,63 +24,62 @@ module Registers(
1624
reg [`FISC_INTEGER_SZ-1:0] esr; /* Exception Syndrome Register */
1725
reg [`FISC_INTEGER_SZ-1:0] elr; /* Exception Link / Return Register */
1826
reg [11:0] cpsr; /* Current Processor Status Register */
19-
reg [11:0] spsr[0:6]; /* Saved Processor Status Register */
27+
reg [11:0] spsr [0:6]; /* Saved Processor Status Register */
2028
reg [`FISC_INTEGER_SZ-1:0] ivp; /* Interrupt Vector Pointer */
2129
reg [`FISC_INTEGER_SZ-1:0] evp; /* Exception Vector Pointer */
2230
reg [`FISC_INTEGER_SZ-1:0] pdp; /* Page Directory Pointer */
2331
reg [`FISC_INTEGER_SZ-1:0] pfla; /* Page Fault Linear Address */
2432

2533
/* Read logic */
26-
assign dout_reg =
27-
(!wr_fromreg && !wr_fromimm) ?
28-
(rd_reg < 32) ? regfile[rd_reg] /* Read from General Purpose registers */
29-
/* Read from all other special registers */
30-
: (rd_reg == 32) ? pc
31-
: (rd_reg == 33) ? esr
32-
: (rd_reg == 34) ? elr
33-
: (rd_reg == 35) ? cpsr
34-
: (rd_reg >= 36 && rd_reg <= 41) ? spsr[rd_reg - 36]
35-
: (rd_reg == 42) ? ivp
36-
: (rd_reg == 43) ? evp
37-
: (rd_reg == 44) ? pdp
38-
: (rd_reg == 45) ? pfla
39-
: 'bZ
34+
assign dout1 =
35+
(rd_reg1 < 32) ? regfile[rd_reg1] /* Read from General Purpose registers */
36+
/* Read from all other special registers */
37+
: (rd_reg1 == 32) ? pc
38+
: (rd_reg1 == 33) ? esr
39+
: (rd_reg1 == 34) ? elr
40+
: (rd_reg1 == 35) ? cpsr
41+
: (rd_reg1 >= 36 && rd_reg1 <= 41) ? spsr[rd_reg1 - 36]
42+
: (rd_reg1 == 42) ? ivp
43+
: (rd_reg1 == 43) ? evp
44+
: (rd_reg1 == 44) ? pdp
45+
: (rd_reg1 == 45) ? pfla
46+
: 'bZ;
47+
48+
assign dout2 =
49+
(rd_reg2 < 32) ? regfile[rd_reg2] /* Read from General Purpose registers */
50+
/* Read from all other special registers */
51+
: (rd_reg2 == 32) ? pc
52+
: (rd_reg2 == 33) ? esr
53+
: (rd_reg2 == 34) ? elr
54+
: (rd_reg2 == 35) ? cpsr
55+
: (rd_reg2 >= 36 && rd_reg2 <= 41) ? spsr[rd_reg2 - 36]
56+
: (rd_reg2 == 42) ? ivp
57+
: (rd_reg2 == 43) ? evp
58+
: (rd_reg2 == 44) ? pdp
59+
: (rd_reg2 == 45) ? pfla
4060
: 'bZ;
4161

4262
/* Write logic */
4363
always@(posedge clk) begin
44-
if(wr_fromreg) begin
45-
/* Write from another register */
46-
if(wr_reg < 32)
47-
regfile[wr_reg] = dout_reg;
48-
else
49-
case(wr_reg)
50-
32: pc = dout_reg;
51-
33: esr = dout_reg;
52-
34: elr = dout_reg;
53-
35: cpsr = dout_reg[11:0];
54-
36,37,38,39,40,41: spsr[wr_reg - 36] = dout_reg[11:0];
55-
42: ivp = dout_reg;
56-
43: evp = dout_reg;
57-
44: pdp = dout_reg;
58-
45: pfla = dout_reg;
59-
endcase
60-
end else if(wr_fromimm) begin
64+
if(wr) begin
6165
/* Write from immediate value */
6266
if(wr_reg < 32)
63-
regfile[wr_reg] = din_reg;
67+
regfile[wr_reg] = din;
6468
else
6569
case(wr_reg)
66-
32: pc = din_reg;
67-
33: esr = din_reg;
68-
34: elr = din_reg;
69-
35: cpsr = din_reg[11:0];
70-
36,37,38,39,40,41: spsr[wr_reg - 36] = din_reg[11:0];
71-
42: ivp = din_reg;
72-
43: evp = din_reg;
73-
44: pdp = din_reg;
74-
45: pfla = din_reg;
70+
32: pc = din;
71+
33: esr = din;
72+
34: elr = din;
73+
35: cpsr = din[11:0];
74+
36,37,38,39,40,41: spsr[wr_reg - 36] = din[11:0];
75+
42: ivp = din;
76+
43: evp = din;
77+
44: pdp = din;
78+
45: pfla = din;
7579
endcase
80+
81+
if(set_flags)
82+
cpsr[11:8] <= {flag_negative, flag_zero, flag_overflow, flag_carry};
7683
end
7784
end
78-
endmodule
85+
endmodule

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