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‎README.md‎

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<p align="center"><a href="http://www.archfisc.com/">FISC-SystemVerilog</a></p>
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# FISC-SystemVerilog
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FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64.
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Please visit http://www.archfisc.com

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/FISC.qpf‎

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2011 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 11.1 Build 259 01/25/2012 Service Pack 2 SJ Full Version
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# Date created = 22:59:44 June 04, 2013
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "11.1"
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DATE = "22:59:44 June 04, 2013"
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# Revisions
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PROJECT_REVISION = "top"

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/Registers.bsf‎

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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2017 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Intel and sold by Intel or its
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authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 232 160)
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(text "Registers" (rect 5 0 43 12)(font "Arial" ))
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(text "inst" (rect 8 128 20 140)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clk" (rect 0 0 10 12)(font "Arial" ))
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(text "clk" (rect 21 27 31 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 0 48)
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(input)
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(text "rd_reg[5..0]" (rect 0 0 47 12)(font "Arial" ))
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(text "rd_reg[5..0]" (rect 21 43 68 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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(pt 0 64)
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(input)
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(text "wr_reg[5..0]" (rect 0 0 48 12)(font "Arial" ))
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(text "wr_reg[5..0]" (rect 21 59 69 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 3))
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)
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(port
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(pt 0 80)
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(input)
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(text "wr_fromreg" (rect 0 0 48 12)(font "Arial" ))
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(text "wr_fromreg" (rect 21 75 69 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80)(line_width 1))
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)
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(port
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(pt 0 96)
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(input)
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(text "wr_fromimm" (rect 0 0 53 12)(font "Arial" ))
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(text "wr_fromimm" (rect 21 91 74 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96)(line_width 1))
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)
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(port
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(pt 0 112)
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(input)
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(text "din_reg[63..0]" (rect 0 0 54 12)(font "Arial" ))
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(text "din_reg[63..0]" (rect 21 107 75 119)(font "Arial" ))
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(line (pt 0 112)(pt 16 112)(line_width 3))
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)
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(port
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(pt 216 32)
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(output)
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(text "dout_reg[63..0]" (rect 0 0 60 12)(font "Arial" ))
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(text "dout_reg[63..0]" (rect 135 27 195 39)(font "Arial" ))
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(line (pt 216 32)(pt 200 32)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 200 128)(line_width 1))
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)
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)

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/fisc_core.bsf‎

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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2017 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Intel and sold by Intel or its
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authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 192 192)
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(text "fisc_core" (rect 5 0 42 12)(font "Arial" ))
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(text "inst" (rect 8 160 20 172)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clk" (rect 0 0 10 12)(font "Arial" ))
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(text "clk" (rect 21 27 31 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 0 48)
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(input)
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(text "int_n" (rect 0 0 18 12)(font "Arial" ))
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(text "int_n" (rect 21 43 39 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 1))
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)
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(port
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(pt 0 64)
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(input)
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(text "nmi_n" (rect 0 0 24 12)(font "Arial" ))
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(text "nmi_n" (rect 21 59 45 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 1))
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)
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(port
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(pt 0 80)
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(input)
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(text "reset_n" (rect 0 0 30 12)(font "Arial" ))
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(text "reset_n" (rect 21 75 51 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80)(line_width 1))
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)
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(port
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(pt 0 96)
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(input)
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(text "wait_n" (rect 0 0 24 12)(font "Arial" ))
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(text "wait_n" (rect 21 91 45 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96)(line_width 1))
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)
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(port
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(pt 176 32)
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(output)
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(text "halt_n" (rect 0 0 23 12)(font "Arial" ))
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(text "halt_n" (rect 132 27 155 39)(font "Arial" ))
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(line (pt 176 32)(pt 160 32)(line_width 1))
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)
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(port
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(pt 176 48)
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(output)
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(text "opcycle_n" (rect 0 0 41 12)(font "Arial" ))
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(text "opcycle_n" (rect 114 43 155 55)(font "Arial" ))
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(line (pt 176 48)(pt 160 48)(line_width 1))
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)
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(port
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(pt 176 64)
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(output)
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(text "ioack_n" (rect 0 0 30 12)(font "Arial" ))
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(text "ioack_n" (rect 125 59 155 71)(font "Arial" ))
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(line (pt 176 64)(pt 160 64)(line_width 1))
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)
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(port
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(pt 176 80)
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(output)
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(text "wr_n" (rect 0 0 20 12)(font "Arial" ))
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(text "wr_n" (rect 135 75 155 87)(font "Arial" ))
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(line (pt 176 80)(pt 160 80)(line_width 1))
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)
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(port
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(pt 176 96)
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(output)
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(text "rd_n" (rect 0 0 18 12)(font "Arial" ))
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(text "rd_n" (rect 137 91 155 103)(font "Arial" ))
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(line (pt 176 96)(pt 160 96)(line_width 1))
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)
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(port
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(pt 176 128)
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(output)
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(text "a[63..0]" (rect 0 0 29 12)(font "Arial" ))
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(text "a[63..0]" (rect 126 123 155 135)(font "Arial" ))
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(line (pt 176 128)(pt 160 128)(line_width 3))
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)
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(port
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(pt 176 112)
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(bidir)
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(text "d[63..0]" (rect 0 0 29 12)(font "Arial" ))
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(text "d[63..0]" (rect 126 107 155 119)(font "Arial" ))
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(line (pt 176 112)(pt 160 112)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 160 160)(line_width 1))
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)
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)

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/greybox_tmp/cbx_args.txt‎

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BANDWIDTH_TYPE=AUTO
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CLK0_DIVIDE_BY=1
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CLK0_DUTY_CYCLE=50
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CLK0_MULTIPLY_BY=10
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CLK0_PHASE_SHIFT=0
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CLK1_DIVIDE_BY=1
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CLK1_DUTY_CYCLE=50
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CLK1_MULTIPLY_BY=20
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CLK1_PHASE_SHIFT=0
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COMPENSATE_CLOCK=CLK0
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INCLK0_INPUT_FREQUENCY=100000
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INTENDED_DEVICE_FAMILY="Cyclone IV E"
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LPM_TYPE=altpll
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OPERATION_MODE=NORMAL
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PLL_TYPE=AUTO
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PORT_ACTIVECLOCK=PORT_UNUSED
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PORT_ARESET=PORT_USED
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PORT_CLKBAD0=PORT_UNUSED
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PORT_CLKBAD1=PORT_UNUSED
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PORT_CLKLOSS=PORT_UNUSED
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PORT_CLKSWITCH=PORT_UNUSED
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PORT_CONFIGUPDATE=PORT_UNUSED
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PORT_FBIN=PORT_UNUSED
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PORT_INCLK0=PORT_USED
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PORT_INCLK1=PORT_UNUSED
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PORT_LOCKED=PORT_USED
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PORT_PFDENA=PORT_UNUSED
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PORT_PHASECOUNTERSELECT=PORT_UNUSED
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PORT_PHASEDONE=PORT_UNUSED
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PORT_PHASESTEP=PORT_UNUSED
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PORT_PHASEUPDOWN=PORT_UNUSED
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PORT_PLLENA=PORT_UNUSED
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PORT_SCANACLR=PORT_UNUSED
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PORT_SCANCLK=PORT_UNUSED
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PORT_SCANCLKENA=PORT_UNUSED
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PORT_SCANDATA=PORT_UNUSED
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PORT_SCANDATAOUT=PORT_UNUSED
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PORT_SCANDONE=PORT_UNUSED
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PORT_SCANREAD=PORT_UNUSED
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PORT_SCANWRITE=PORT_UNUSED
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PORT_clk0=PORT_USED
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PORT_clk1=PORT_USED
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PORT_clk2=PORT_UNUSED
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PORT_clk3=PORT_UNUSED
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PORT_clk4=PORT_UNUSED
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PORT_clk5=PORT_UNUSED
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PORT_clkena0=PORT_UNUSED
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PORT_clkena1=PORT_UNUSED
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PORT_clkena2=PORT_UNUSED
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PORT_clkena3=PORT_UNUSED
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PORT_clkena4=PORT_UNUSED
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PORT_clkena5=PORT_UNUSED
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PORT_extclk0=PORT_UNUSED
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PORT_extclk1=PORT_UNUSED
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PORT_extclk2=PORT_UNUSED
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PORT_extclk3=PORT_UNUSED
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SELF_RESET_ON_LOSS_LOCK=OFF
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WIDTH_CLOCK=5
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DEVICE_FAMILY="Cyclone IV E"
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CBX_AUTO_BLACKBOX=ALL
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areset
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inclk
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inclk
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clk
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clk
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locked

‎fpga/Altera - Cyclone IV E - EP4CE10E22C8/top.asm.rpt‎

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Assembler report for top
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Tue Jul 26 15:58:52 2016
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Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Assembler Summary
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3. Assembler Settings
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4. Assembler Generated Files
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5. Assembler Device Options: C:/Users/Miguel/Desktop/Cyclone IV/CycloneIV_TemplateProject/top.sof
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6. Assembler Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
24+
functions, and any output files from any of the foregoing
25+
(including device programming or simulation files), and any
26+
associated documentation or information are expressly subject
27+
to the terms and conditions of the Altera Program License
28+
Subscription Agreement, the Altera Quartus Prime License Agreement,
29+
the Altera MegaCore Function License Agreement, or other
30+
applicable license agreement, including, without limitation,
31+
that your use is for the sole purpose of programming logic
32+
devices manufactured by Altera and sold by Altera or its
33+
authorized distributors. Please refer to the applicable
34+
agreement for further details.
35+
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+---------------------------------------------------------------+
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; Assembler Summary ;
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+-----------------------+---------------------------------------+
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; Assembler Status ; Successful - Tue Jul 26 15:58:52 2016 ;
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; Revision Name ; top ;
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; Top-level Entity Name ; top ;
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; Family ; Cyclone IV E ;
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; Device ; EP4CE6E22C8 ;
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+-----------------------+---------------------------------------+
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+----------------------------------+
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; Assembler Settings ;
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+--------+---------+---------------+
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; Option ; Setting ; Default Value ;
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+--------+---------+---------------+
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+----------------------------------------------------------------------+
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; Assembler Generated Files ;
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+----------------------------------------------------------------------+
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; File Name ;
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+----------------------------------------------------------------------+
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; C:/Users/Miguel/Desktop/Cyclone IV/CycloneIV_TemplateProject/top.sof ;
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+----------------------------------------------------------------------+
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+------------------------------------------------------------------------------------------------+
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; Assembler Device Options: C:/Users/Miguel/Desktop/Cyclone IV/CycloneIV_TemplateProject/top.sof ;
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+----------------+-------------------------------------------------------------------------------+
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; Option ; Setting ;
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+----------------+-------------------------------------------------------------------------------+
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; Device ; EP4CE6E22C8 ;
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; JTAG usercode ; 0x00092F71 ;
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; Checksum ; 0x00092F71 ;
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+----------------+-------------------------------------------------------------------------------+
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+--------------------+
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; Assembler Messages ;
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+--------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Assembler
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Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
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Info: Processing started: Tue Jul 26 15:58:50 2016
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Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off project -c top
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Info (115031): Writing out detailed assembly data for power analysis
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Info (115030): Assembler is generating device programming files
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Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 755 megabytes
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Info: Processing ended: Tue Jul 26 15:58:53 2016
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Info: Elapsed time: 00:00:03
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Info: Total CPU time (on all processors): 00:00:02
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