fix integration test errors

Author: flavius-t

src/edgepi/adc/edgepi_adc.py

@@ -341,13 +341,13 @@ def start_conversions(self):
         filter_mode = state.filter_mode.code
 
         conv_delay = expected_initial_time_delay(
-            adc_num, data_rate.value.op_code, filter_mode.value.opcode
+            adc_num, data_rate.value.op_code, filter_mode.value.op_code
         )
         _logger.debug(
             (
                 f"\nComputed time delay = {conv_delay} (ms) with the following config opcodes:\n"
-                f"adc_num={adc_num}, conv_mode={hex(conv_mode)}, "
-                f"data_rate={hex(data_rate)} filter_mode={hex(filter_mode)}\n"
+                f"adc_num={adc_num}, conv_mode={hex(conv_mode.value.op_code)}, "
+                f"data_rate={hex(data_rate.value.op_code)} filter_mode={hex(filter_mode.value.op_code)}\n"
             )
         )
         self.__send_start_command(adc_num)
@@ -419,7 +419,7 @@ def read_voltage(self):
         _logger.debug(
             (
                 f"\nContinuous time delay = {delay} (ms) with the following config opcodes:\n"
-                f"adc_num={adc},  data_rate={hex(data_rate)}\n"
+                f"adc_num={adc},  data_rate={hex(data_rate.value.op_code)}\n"
             )
         )
         time.sleep(delay / 1000)

src/test_edgepi/integration_tests/test_adc/test_adc.py

@@ -804,4 +804,4 @@ def test_select_differential(adc_num, diff, mux_reg, mux_reg_val, adc):
 def test_rtd_mode(enable, adc):
     # TODO: pass if no error raised for now, check RTD is on once get_state is implemented
     adc.rtd_mode(enable=enable)
-    assert adc.get_state().rtd_on.value
+    assert adc.get_state().rtd_on.value == enable