forked from dotnet/coreclr
-
Notifications
You must be signed in to change notification settings - Fork 0
/
emitarm.cpp
7891 lines (6842 loc) · 234 KB
/
emitarm.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
//
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX emitArm.cpp XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#if defined(_TARGET_ARM_)
/*****************************************************************************/
/*****************************************************************************/
#include "instr.h"
#include "emit.h"
#include "codegen.h"
/*****************************************************************************/
const instruction emitJumpKindInstructions[] =
{
INS_nop,
#define JMP_SMALL(en, rev, ins, condcode) INS_##ins,
#include "emitjmps.h"
};
const emitJumpKind emitReverseJumpKinds[] =
{
EJ_NONE,
#define JMP_SMALL(en, rev, ins, condcode) EJ_##rev,
#include "emitjmps.h"
};
const unsigned emitJumpKindCondCodes[] =
{
15, // illegal
#define JMP_SMALL(en, rev, ins, condcode) condcode,
#include "emitjmps.h"
};
/*****************************************************************************
* Look up the instruction for a jump kind
*/
/*static*/ instruction emitter::emitJumpKindToIns(emitJumpKind jumpKind)
{
assert((unsigned)jumpKind < ArrLen(emitJumpKindInstructions));
return emitJumpKindInstructions[jumpKind];
}
/*****************************************************************************
* Look up the jump kind for an instruction. It better be a conditional
* branch instruction with a jump kind!
*/
/*static*/ emitJumpKind emitter::emitInsToJumpKind(instruction ins)
{
for (unsigned i = 0; i < ArrLen(emitJumpKindInstructions); i++)
{
if (ins == emitJumpKindInstructions[i])
{
emitJumpKind ret = (emitJumpKind)i;
assert(EJ_NONE < ret && ret < EJ_COUNT);
return ret;
}
}
unreached();
}
/*****************************************************************************
* Reverse the conditional jump
*/
/*static*/ emitJumpKind emitter::emitReverseJumpKind(emitJumpKind jumpKind)
{
assert(jumpKind < EJ_COUNT);
return emitReverseJumpKinds[jumpKind];
}
/*****************************************************************************
* Look up the condition code for a give jump kind
*/
/*static*/ unsigned emitter::emitJumpKindCondCode(emitJumpKind jumpKind)
{
assert(EJ_NONE < jumpKind && jumpKind < EJ_COUNT);
return emitJumpKindCondCodes[jumpKind];
}
/*****************************************************************************
*
* Return the allocated size (in bytes) of the given instruction descriptor.
*/
size_t emitter::emitSizeOfInsDsc(instrDesc *id)
{
assert (!emitIsTinyInsDsc(id));
if (emitIsScnsInsDsc(id))
return SMALL_IDSC_SIZE;
assert((unsigned)id->idInsFmt() < emitFmtCount);
ID_OPS idOp = (ID_OPS) emitFmtToOps[id->idInsFmt()];
bool isCallIns = (id->idIns() == INS_bl) || (id->idIns() == INS_blx);
bool maybeCallIns = (id->idIns() == INS_b) || (id->idIns() == INS_bx);
// An INS_call instruction may use a "fat" direct/indirect call descriptor
// except for a local call to a label (i.e. call to a finally).
// Only ID_OP_CALL and ID_OP_SPEC check for this, so we enforce that the
// INS_call instruction always uses one of these idOps.
assert(!isCallIns || // either not a call or
idOp == ID_OP_CALL || // is a direct call
idOp == ID_OP_SPEC || // is an indirect call
idOp == ID_OP_JMP ); // is a local call to finally clause
switch (idOp)
{
case ID_OP_NONE:
break;
case ID_OP_JMP:
return sizeof(instrDescJmp);
case ID_OP_LBL:
return sizeof(instrDescLbl);
case ID_OP_CALL:
case ID_OP_SPEC:
assert(isCallIns || maybeCallIns);
if (id->idIsLargeCall())
{
/* Must be a "fat" indirect call descriptor */
return sizeof(instrDescCGCA);
}
else
{
assert(!id->idIsLargeDsp());
assert(!id->idIsLargeCns());
return sizeof(instrDesc);
}
break;
default:
NO_WAY("unexpected instruction descriptor format");
break;
}
if (id->idIsLargeCns())
{
if (id->idIsLargeDsp())
return sizeof(instrDescCnsDsp);
else
return sizeof(instrDescCns);
}
else
{
if (id->idIsLargeDsp())
return sizeof(instrDescDsp);
else
return sizeof(instrDesc);
}
}
bool offsetFitsInVectorMem(int disp)
{
unsigned imm = unsigned_abs(disp);
return ((imm & 0x03fc) == imm);
}
#ifdef DEBUG
/*****************************************************************************
*
* The following called for each recorded instruction -- use for debugging.
*/
void emitter::emitInsSanityCheck(instrDesc *id)
{
/* What instruction format have we got? */
switch (id->idInsFmt())
{
case IF_T1_A: // T1_A ................
case IF_T2_A: // T2_A ................ ................
break;
case IF_T1_B: // T1_B ........cccc.... cond
case IF_T2_B: // T2_B ................ ............iiii imm4
assert(emitGetInsSC(id) < 0x10);
break;
case IF_T1_C: // T1_C .....iiiiinnnddd R1 R2 imm5
assert(isLowRegister(id->idReg1()));
assert(isLowRegister(id->idReg2()));
if (emitInsIsLoadOrStore(id->idIns()))
{
emitAttr size = id->idOpSize();
int imm = emitGetInsSC(id);
imm = insUnscaleImm(imm, size);
assert(imm < 0x20);
}
else
{
assert(id->idSmallCns() < 0x20);
}
break;
case IF_T1_D0: // T1_D0 ........Dmmmmddd R1* R2*
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
break;
case IF_T1_D1: // T1_D1 .........mmmm... R1*
assert(isGeneralRegister(id->idReg1()));
break;
case IF_T1_D2: // T1_D2 .........mmmm... R3*
assert(isGeneralRegister(id->idReg3()));
break;
case IF_T1_E: // T1_E ..........nnnddd R1 R2
assert(isLowRegister(id->idReg1()));
assert(isLowRegister(id->idReg2()));
assert(id->idSmallCns() < 0x20);
break;
case IF_T1_F: // T1_F .........iiiiiii SP imm7
assert(id->idReg1() == REG_SP);
assert(id->idOpSize() == EA_4BYTE);
assert((emitGetInsSC(id) & ~0x1FC) == 0);
break;
case IF_T1_G: // T1_G .......iiinnnddd R1 R2 imm3
assert(isLowRegister(id->idReg1()));
assert(isLowRegister(id->idReg2()));
assert(id->idSmallCns() < 0x8);
break;
case IF_T1_H: // T1_H .......mmmnnnddd R1 R2 R3
assert(isLowRegister(id->idReg1()));
assert(isLowRegister(id->idReg2()));
assert(isLowRegister(id->idReg3()));
break;
case IF_T1_I: // T1_I ......i.iiiiiddd R1 imm6
assert(isLowRegister(id->idReg1()));
break;
case IF_T1_J0: // T1_J0 .....dddiiiiiiii R1 imm8
assert(isLowRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T1_J1: // T1_J1 .....dddiiiiiiii R1 <regmask8>
assert(isLowRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T1_J2: // T1_J2 .....dddiiiiiiii R1 SP imm8
assert(isLowRegister(id->idReg1()));
assert(id->idReg2() == REG_SP);
assert(id->idOpSize() == EA_4BYTE);
assert((emitGetInsSC(id)& ~0x3FC) == 0);
break;
case IF_T1_L0: // T1_L0 ........iiiiiiii imm8
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T1_L1: // T1_L1 .......Rrrrrrrrr <regmask8+2>
assert(emitGetInsSC(id) < 0x400);
break;
case IF_T2_C0: // T2_C0 ...........Snnnn .iiiddddiishmmmm R1 R2 R3 S, imm5, sh
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(emitGetInsSC(id) < 0x20);
break;
case IF_T2_C4: // T2_C4 ...........Snnnn ....dddd....mmmm R1 R2 R3 S
case IF_T2_C5: // T2_C5 ............nnnn ....dddd....mmmm R1 R2 R3
case IF_T2_G1: // T2_G1 ............nnnn ttttTTTT........ R1 R2 R3
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
break;
case IF_T2_C1: // T2_C1 ...........S.... .iiiddddiishmmmm R1 R2 S, imm5, sh
case IF_T2_C2: // T2_C2 ...........S.... .iiiddddii..mmmm R1 R2 S, imm5
case IF_T2_C8: // T2_C8 ............nnnn .iii....iishmmmm R1 R2 imm5, sh
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(emitGetInsSC(id) < 0x20);
break;
case IF_T2_C6: // T2_C6 ................ ....dddd..iimmmm R1 R2 imm2
case IF_T2_C7: // T2_C7 ............nnnn ..........shmmmm R1 R2 imm2
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(emitGetInsSC(id) < 0x4);
break;
case IF_T2_C3: // T2_C3 ...........S.... ....dddd....mmmm R1 R2 S
case IF_T2_C9: // T2_C9 ............nnnn ............mmmm R1 R2
case IF_T2_C10: // T2_C10 ............mmmm ....dddd....mmmm R1 R2
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
break;
case IF_T2_D0: // T2_D0 ............nnnn .iiiddddii.wwwww R1 R2 imm5, imm5
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(emitGetInsSC(id) < 0x400);
break;
case IF_T2_D1: // T2_D1 ................ .iiiddddii.wwwww R1 imm5, imm5
assert(isGeneralRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x400);
break;
case IF_T2_E0: // T2_E0 ............nnnn tttt......shmmmm R1 R2 R3 imm2
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
if (id->idIsLclVar())
{
assert(isGeneralRegister(codeGen->rsGetRsvdReg()));
}
else
{
assert(isGeneralRegister(id->idReg3()));
assert(emitGetInsSC(id) < 0x4);
}
break;
case IF_T2_E1: // T2_E1 ............nnnn tttt............ R1 R2
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
break;
case IF_T2_E2: // T2_E2 ................ tttt............ R1
assert(isGeneralRegister(id->idReg1()));
break;
case IF_T2_F1: // T2_F1 ............nnnn ttttdddd....mmmm R1 R2 R3 R4
case IF_T2_F2: // T2_F2 ............nnnn aaaadddd....mmmm R1 R2 R3 R4
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(isGeneralRegister(id->idReg4()));
break;
case IF_T2_G0: // T2_G0 .......PU.W.nnnn ttttTTTTiiiiiiii R1 R2 R3 imm8, PUW
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(unsigned_abs(emitGetInsSC(id)) < 0x100);
break;
case IF_T2_H0: // T2_H0 ............nnnn tttt.PUWiiiiiiii R1 R2 imm8, PUW
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(unsigned_abs(emitGetInsSC(id)) < 0x100);
break;
case IF_T2_H1: // T2_H1 ............nnnn tttt....iiiiiiii R1 R2 imm8
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T2_H2: // T2_H2 ............nnnn ........iiiiiiii R1 imm8
assert(isGeneralRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T2_I0: // T2_I0 ..........W.nnnn rrrrrrrrrrrrrrrr R1 W, imm16
assert(isGeneralRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x10000);
break;
case IF_T2_N: // T2_N .....i......iiii .iiiddddiiiiiiii R1 imm16
assert(isGeneralRegister(id->idReg1()));
break;
case IF_T2_N2: // T2_N2 .....i......iiii .iiiddddiiiiiiii R1 imm16
assert(isGeneralRegister(id->idReg1()));
assert((size_t)emitGetInsSC(id) < emitDataSize());
break;
case IF_T2_I1: // T2_I1 ................ rrrrrrrrrrrrrrrr imm16
assert(emitGetInsSC(id) < 0x10000);
break;
case IF_T2_K1: // T2_K1 ............nnnn ttttiiiiiiiiiiii R1 R2 imm12
case IF_T2_M0: // T2_M0 .....i......nnnn .iiiddddiiiiiiii R1 R2 imm12
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(emitGetInsSC(id) < 0x1000);
break;
case IF_T2_L0: // T2_L0 .....i.....Snnnn .iiiddddiiiiiiii R1 R2 S, imm8<<imm4
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isModImmConst(emitGetInsSC(id)));
break;
case IF_T2_K4: // T2_K4 ........U....... ttttiiiiiiiiiiii R1 PC U, imm12
case IF_T2_M1: // T2_M1 .....i.......... .iiiddddiiiiiiii R1 PC imm12
assert(isGeneralRegister(id->idReg1()));
assert(id->idReg2() == REG_PC);
assert(emitGetInsSC(id) < 0x1000);
break;
case IF_T2_K3: // T2_K3 ........U....... ....iiiiiiiiiiii PC U, imm12
assert(id->idReg1() == REG_PC);
assert(emitGetInsSC(id) < 0x1000);
break;
case IF_T2_K2: // T2_K2 ............nnnn ....iiiiiiiiiiii R1 imm12
assert(isGeneralRegister(id->idReg1()));
assert(emitGetInsSC(id) < 0x1000);
break;
case IF_T2_L1: // T2_L1 .....i.....S.... .iiiddddiiiiiiii R1 S, imm8<<imm4
case IF_T2_L2: // T2_L2 .....i......nnnn .iii....iiiiiiii R1 imm8<<imm4
assert(isGeneralRegister(id->idReg1()));
assert(isModImmConst(emitGetInsSC(id)));
break;
case IF_T1_J3: // T1_J3 .....dddiiiiiiii R1 PC imm8
assert(isGeneralRegister(id->idReg1()));
assert(id->idReg2() == REG_PC);
assert(emitGetInsSC(id) < 0x100);
break;
case IF_T1_K: // T1_K ....cccciiiiiiii Branch imm8, cond4
case IF_T1_M: // T1_M .....iiiiiiiiiii Branch imm11
case IF_T2_J1: // T2_J1 .....Scccciiiiii ..j.jiiiiiiiiiii Branch imm20, cond4
case IF_T2_J2: // T2_J2 .....Siiiiiiiiii ..j.jiiiiiiiiii. Branch imm24
case IF_T2_N1: // T2_N .....i......iiii .iiiddddiiiiiiii R1 imm16
case IF_T2_J3: // T2_J3 .....Siiiiiiiiii ..j.jiiiiiiiiii. Call imm24
case IF_LARGEJMP:
break;
case IF_T2_VFP3:
if (id->idOpSize() == EA_8BYTE)
{
assert(isDoubleReg(id->idReg1()));
assert(isDoubleReg(id->idReg2()));
assert(isDoubleReg(id->idReg3()));
}
else
{
assert(id->idOpSize() == EA_4BYTE);
assert(isFloatReg(id->idReg1()));
assert(isFloatReg(id->idReg2()));
assert(isFloatReg(id->idReg3()));
}
break;
case IF_T2_VFP2:
assert(isFloatReg(id->idReg1()));
assert(isFloatReg(id->idReg2()));
break;
case IF_T2_VLDST:
if (id->idOpSize() == EA_8BYTE)
assert(isDoubleReg(id->idReg1()));
else
assert(isFloatReg(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(offsetFitsInVectorMem(emitGetInsSC(id)));
break;
case IF_T2_VMOVD:
assert(id->idOpSize() == EA_8BYTE);
if (id->idIns() == INS_vmov_d2i)
{
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isDoubleReg(id->idReg3()));
}
else
{
assert(id->idIns() == INS_vmov_i2d);
assert(isDoubleReg(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
}
break;
case IF_T2_VMOVS:
assert(id->idOpSize() == EA_4BYTE);
if (id->idIns() == INS_vmov_i2f)
{
assert(isFloatReg(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
}
else
{
assert(id->idIns() == INS_vmov_f2i);
assert(isGeneralRegister(id->idReg1()));
assert(isFloatReg(id->idReg2()));
}
break;
default:
printf("unexpected format %s\n", emitIfName(id->idInsFmt()));
assert(!"Unexpected format");
break;
}
}
#endif // DEBUG
bool emitter::emitInsMayWriteToGCReg(instrDesc *id)
{
instruction ins = id->idIns();
insFormat fmt = id->idInsFmt();
switch (fmt)
{
// These are the formats with "destination" or "target" registers:
case IF_T1_C: case IF_T1_D0: case IF_T1_E: case IF_T1_G: case IF_T1_H:
case IF_T1_J0: case IF_T1_J1: case IF_T1_J2: case IF_T1_J3:
case IF_T2_C0: case IF_T2_C1: case IF_T2_C2: case IF_T2_C3: case IF_T2_C4: case IF_T2_C5: case IF_T2_C6: case IF_T2_C10:
case IF_T2_D0: case IF_T2_D1: case IF_T2_F1: case IF_T2_F2:
case IF_T2_L0: case IF_T2_L1: case IF_T2_M0: case IF_T2_M1:
case IF_T2_N: case IF_T2_N1: case IF_T2_N2: case IF_T2_VFP3: case IF_T2_VFP2: case IF_T2_VLDST:
case IF_T2_E0: case IF_T2_E1: case IF_T2_E2:
case IF_T2_G0: case IF_T2_G1: case IF_T2_H0: case IF_T2_H1:
case IF_T2_K1: case IF_T2_K4:
// Some formats with "destination" or "target" registers are actually used for store instructions, for the "source" value
// written to memory.
// Similarly, PUSH has a target register, indicating the start of the set of registers to push. POP
// *does* write to at least one register, so we do not make that a special case.
// Various compare/test instructions do not write (except to the flags). Technically "teq" does not need to be
// be in this list because it has no forms matched above, but I'm putting it here for completeness.
switch (ins)
{
case INS_str: case INS_strb: case INS_strh: case INS_strd:
case INS_strex: case INS_strexb: case INS_strexd: case INS_strexh:
case INS_push:
case INS_cmp: case INS_cmn: case INS_tst: case INS_teq:
return false;
default:
return true;
}
case IF_T2_VMOVS:
// VMOV.i2f reads from the integer register. Conversely VMOV.f2i writes to GC pointer-sized
// integer register that might have previously held GC pointers, so they need to be included.
assert(id->idGCref() == GCT_NONE);
return (ins == INS_vmov_f2i);
case IF_T2_VMOVD:
// VMOV.i2d reads from the integer registers. Conversely VMOV.d2i writes to GC pointer-sized
// integer registers that might have previously held GC pointers, so they need to be included.
assert(id->idGCref() == GCT_NONE);
return (ins == INS_vmov_d2i);
default:
return false;
}
}
bool emitter::emitInsWritesToLclVarStackLoc(instrDesc *id)
{
if (!id->idIsLclVar())
return false;
instruction ins = id->idIns();
// This list is related to the list of instructions used to store local vars in emitIns_S_R().
// We don't accept writing to float local vars.
switch (ins)
{
case INS_strb:
case INS_strh:
case INS_str:
return true;
default:
return false;
}
}
bool emitter::emitInsMayWriteMultipleRegs(instrDesc *id)
{
instruction ins = id->idIns();
switch (ins)
{
case INS_ldm: case INS_ldmdb:
case INS_pop:
case INS_smlal:
case INS_smull:
case INS_umlal:
case INS_umull:
case INS_vmov_d2i:
return true;
default:
return false;
}
}
/*****************************************************************************/
#ifdef DEBUG
/*****************************************************************************
*
* Return a string that represents the given register.
*/
const char * emitter::emitRegName(regNumber reg, emitAttr attr, bool varName)
{
assert(reg < REG_COUNT);
const char * rn = emitComp->compRegVarName(reg, varName, false);
assert(strlen(rn) >= 1);
return rn;
}
const char *emitter::emitFloatRegName(regNumber reg, emitAttr attr, bool varName)
{
assert(reg < REG_COUNT);
const char * rn = emitComp->compRegVarName(reg, varName, true);
assert(strlen(rn) >= 1);
return rn;
}
#endif // DEBUG
/*****************************************************************************
*
* Returns the base encoding of the given CPU instruction.
*/
emitter::insFormat emitter::emitInsFormat(instruction ins)
{
const static insFormat insFormats[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 ) fmt,
#define INST2(id, nm, fp, ldst, fmt, e1, e2 ) fmt,
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) fmt,
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) fmt,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) fmt,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) fmt,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) fmt,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) fmt,
#include "instrs.h"
};
assert(ins < ArrLen(insFormats));
assert((insFormats[ins] != IF_NONE));
return insFormats[ins];
}
// INST_FP is 1
#define LD 2
#define ST 4
#define CMP 8
/*static*/ const BYTE CodeGenInterface::instInfo[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 ) ldst | INST_FP*fp,
#define INST2(id, nm, fp, ldst, fmt, e1, e2 ) ldst | INST_FP*fp,
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) ldst | INST_FP*fp,
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) ldst | INST_FP*fp,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) ldst | INST_FP*fp,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) ldst | INST_FP*fp,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) ldst | INST_FP*fp,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) ldst | INST_FP*fp,
#include "instrs.h"
};
/*****************************************************************************
*
* Returns true if the instruction is some kind of load instruction
*/
bool emitter::emitInsIsLoad(instruction ins)
{
// We have pseudo ins like lea which are not included in emitInsLdStTab.
if (ins < ArrLen(CodeGenInterface::instInfo))
return (CodeGenInterface::instInfo[ins] & LD) ? true : false;
else
return false;
}
/*****************************************************************************
*
* Returns true if the instruction is some kind of compare or test instruction
*/
bool emitter::emitInsIsCompare(instruction ins)
{
// We have pseudo ins like lea which are not included in emitInsLdStTab.
if (ins < ArrLen(CodeGenInterface::instInfo))
return (CodeGenInterface::instInfo[ins] & CMP) ? true : false;
else
return false;
}
/*****************************************************************************
*
* Returns true if the instruction is some kind of store instruction
*/
bool emitter::emitInsIsStore(instruction ins)
{
// We have pseudo ins like lea which are not included in emitInsLdStTab.
if (ins < ArrLen(CodeGenInterface::instInfo))
return (CodeGenInterface::instInfo[ins] & ST) ? true : false;
else
return false;
}
/*****************************************************************************
*
* Returns true if the instruction is some kind of load/store instruction
*/
bool emitter::emitInsIsLoadOrStore(instruction ins)
{
// We have pseudo ins like lea which are not included in emitInsLdStTab.
if (ins < ArrLen(CodeGenInterface::instInfo))
return (CodeGenInterface::instInfo[ins] & (LD|ST)) ? true : false;
else
return false;
}
#undef LD
#undef ST
#undef CMP
/*****************************************************************************
*
* Returns the specific encoding of the given CPU instruction and format
*/
size_t emitter::emitInsCode(instruction ins, insFormat fmt)
{
const static size_t insCodes1[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 ) e1,
#define INST2(id, nm, fp, ldst, fmt, e1, e2 ) e1,
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) e1,
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) e1,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) e1,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e1,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e1,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e1,
#include "instrs.h"
};
const static size_t insCodes2[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 ) e2,
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) e2,
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) e2,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) e2,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e2,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e2,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e2,
#include "instrs.h"
};
const static size_t insCodes3[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) e3,
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) e3,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) e3,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e3,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e3,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e3,
#include "instrs.h"
};
const static size_t insCodes4[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) e4,
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) e4,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e4,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e4,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e4,
#include "instrs.h"
};
const static size_t insCodes5[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 )
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) e5,
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e5,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e5,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e5,
#include "instrs.h"
};
const static size_t insCodes6[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 )
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 )
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) e6,
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e6,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e6,
#include "instrs.h"
};
const static size_t insCodes7[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 )
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 )
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 )
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e7,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e7,
#include "instrs.h"
};
const static size_t insCodes8[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 )
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 )
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 )
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) e8,
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e8,
#include "instrs.h"
};
const static size_t insCodes9[] =
{
#define INST1(id, nm, fp, ldst, fmt, e1 )
#define INST2(id, nm, fp, ldst, fmt, e1, e2 )
#define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 )
#define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 )
#define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 )
#define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 )
#define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 )
#define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) e9,
#include "instrs.h"
};
const static insFormat formatEncode9[9] = { IF_T1_D0, IF_T1_H, IF_T1_J0, IF_T1_G, IF_T2_L0, IF_T2_C0, IF_T1_F, IF_T1_J2, IF_T1_J3 };
const static insFormat formatEncode8[8] = { IF_T1_H, IF_T1_C, IF_T2_E0, IF_T2_H0, IF_T2_K1, IF_T2_K4, IF_T1_J2, IF_T1_J3 };
const static insFormat formatEncode6A[6] = { IF_T1_H, IF_T1_C, IF_T2_E0, IF_T2_H0, IF_T2_K1, IF_T2_K4};
const static insFormat formatEncode6B[6] = { IF_T1_H, IF_T1_C, IF_T2_E0, IF_T2_H0, IF_T2_K1, IF_T1_J2 };
const static insFormat formatEncode5A[5] = { IF_T1_E, IF_T1_D0, IF_T1_J0, IF_T2_L1, IF_T2_C3 };
const static insFormat formatEncode5B[5] = { IF_T1_E, IF_T1_D0, IF_T1_J0, IF_T2_L2, IF_T2_C8 };
const static insFormat formatEncode4A[4] = { IF_T1_E, IF_T1_C, IF_T2_C4, IF_T2_C2 };
const static insFormat formatEncode4B[4] = { IF_T2_K2, IF_T2_H2, IF_T2_C7, IF_T2_K3 };
const static insFormat formatEncode3A[3] = { IF_T1_E, IF_T2_C0, IF_T2_L0 };
const static insFormat formatEncode3B[3] = { IF_T1_E, IF_T2_C8, IF_T2_L2 };
const static insFormat formatEncode3C[3] = { IF_T1_E, IF_T2_C1, IF_T2_L1 };
const static insFormat formatEncode3D[3] = { IF_T1_L1, IF_T2_E2, IF_T2_I1 };
const static insFormat formatEncode3E[3] = { IF_T2_N, IF_T2_N1, IF_T2_N2 };
const static insFormat formatEncode3F[3] = { IF_T1_M, IF_T2_J2, IF_T2_J3 };
const static insFormat formatEncode2A[2] = { IF_T1_K, IF_T2_J1 };
const static insFormat formatEncode2B[2] = { IF_T1_D1, IF_T1_D2 };
const static insFormat formatEncode2C[2] = { IF_T1_D2, IF_T2_J3 };
const static insFormat formatEncode2D[2] = { IF_T1_J1, IF_T2_I0 };
const static insFormat formatEncode2E[2] = { IF_T1_E, IF_T2_C6 };
const static insFormat formatEncode2F[2] = { IF_T1_E, IF_T2_C5 };
const static insFormat formatEncode2G[2] = { IF_T1_J3, IF_T2_M1 };
size_t code = BAD_CODE;
insFormat insFmt = emitInsFormat(ins);
bool found = false;
int index = 0;
switch (insFmt)
{
case IF_EN9:
for (index=0; index<9; index++)
{
if (fmt == formatEncode9[index])
{
found = true;
break;
}
}
break;
case IF_EN8:
for (index=0; index<8; index++)
{
if (fmt == formatEncode8[index])
{
found = true;
break;
}
}
break;
case IF_EN6A:
for (index=0; index<6; index++)
{
if (fmt == formatEncode6A[index])
{
found = true;
break;
}
}
break;
case IF_EN6B:
for (index=0; index<6; index++)
{
if (fmt == formatEncode6B[index])
{
found = true;
break;
}
}
break;
case IF_EN5A:
for (index=0; index<5; index++)
{
if (fmt == formatEncode5A[index])
{
found = true;
break;
}
}
break;
case IF_EN5B:
for (index=0; index<5; index++)
{
if (fmt == formatEncode5B[index])
{
found = true;
break;
}
}
break;
case IF_EN4A:
for (index=0; index<4; index++)
{
if (fmt == formatEncode4A[index])
{
found = true;
break;
}
}
break;
case IF_EN4B:
for (index=0; index<4; index++)
{
if (fmt == formatEncode4B[index])
{
found = true;
break;
}
}
break;
case IF_EN3A:
for (index=0; index<3; index++)
{
if (fmt == formatEncode3A[index])
{
found = true;
break;
}
}