RAM4K.hdl

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM4K.hdl

/**
 * Memory of 4K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then
 * the in value is loaded into the memory location specified by address
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM4K {
    IN in[16], load, address[12];
    OUT out[16];

    PARTS:
    // Put your code here:
    DMux8Way(in=load, sel=address[9..11], a=tmpa, b=tmpb, c=tmpc, d=tmpd, e=tmpe, f=tmpf, g=tmpg, h=tmph);

    RAM512(in=in, load=tmpa, address=address[0..8], out=tmpa2);
    RAM512(in=in, load=tmpb, address=address[0..8], out=tmpb2);
    RAM512(in=in, load=tmpc, address=address[0..8], out=tmpc2);
    RAM512(in=in, load=tmpd, address=address[0..8], out=tmpd2);
    RAM512(in=in, load=tmpe, address=address[0..8], out=tmpe2);
    RAM512(in=in, load=tmpf, address=address[0..8], out=tmpf2);
    RAM512(in=in, load=tmpg, address=address[0..8], out=tmpg2);
    RAM512(in=in, load=tmph, address=address[0..8], out=tmph2);

    Mux8Way16(a=tmpa2, b=tmpb2, c=tmpc2, d=tmpd2, e=tmpe2, f=tmpf2, g=tmpg2, h=tmph2, sel=address[9..11], out=out);
}