Tpm sci

src/mainboard/protectli/vault_adl_n/variants/vp2430/gpio.c

@@ -732,8 +732,8 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E12 - GPIO */
 	PAD_NC(GPP_E12, NONE),
 
-	/* GPP_E13 - GPIO */
-	PAD_CFG_GPI_APIC_LOW(GPP_E13, NONE, PLTRST),
+	/* GPP_E13 - TPM_PIRQ */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E13, NONE, LEVEL, INVERT, LOCK_CONFIG),
 
 	/* GPP_E14 - DDSP_HPDA */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),

src/mainboard/protectli/vault_adl_n/variants/vp32xx/gpio.c

@@ -416,8 +416,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E10, NONE),
 	PAD_NC(GPP_E11, NONE),
 	PAD_NC(GPP_E12, NONE),
-	/* GPP_E13 - GPIO */
-	PAD_CFG_GPI_APIC_LOW(GPP_E13, NONE, PLTRST),
+	/* GPP_E13 - TPM_PIRQ */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E13, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* GPP_E14 - DDSP_HPDA */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	PAD_NC(GPP_E15, NONE),

src/mainboard/protectli/vault_ehl/Kconfig

@@ -62,4 +62,7 @@ config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT
 
 endif
 
+config TPM_PIRQ
+	default 0x6B # GPP_G19_IRQ
+
 endif # BOARD_PROTECTLI_VP2420

src/mainboard/protectli/vault_ehl/devicetree.cb

@@ -19,9 +19,9 @@ chip soc/intel/elkhartlake
 	# route, i.e., if this route changes then the affected GPE
 	# offset bits also need to be changed. This sets the PMC register
 	# GPE_CFG fields.
-	#register "pmc_gpe0_dw1" = "PMC_GPE_SCC_63_32"
-	#register "pmc_gpe0_dw2" = "PMC_GPE_N_31_0"
-	#register "pmc_gpe0_dw3" = "PMC_GPE_SCC_31_0"
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
 
 	register "tcc_offset" = "5" # TCC of 95C
 
@@ -207,7 +207,7 @@ chip soc/intel/elkhartlake
 				device pnp 2e.a off end # CIR
 			end
 			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
+				device pnp 0.0 on end
 			end
 		end
 		device pci 1f.1 on	end # P2SB

src/soc/intel/elkhartlake/gpio.c

@@ -226,7 +226,6 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 		{ PMC_GPP_C, GPP_C },
 		{ PMC_GPP_E, GPP_E },
 		{ PMC_GPP_G, GPP_G },
-		{ PMC_GPP_S, GPP_S }
 	};
 
 	*num = ARRAY_SIZE(routes);

src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h

@@ -10,19 +10,18 @@
  */
 #define GPP_B			0x0
 #define GPP_T			0x1
-#define GPP_D			0x2
-#define GPP_A			0x3
-#define GPP_R			0x4
+#define GPP_A			0x2
+#define GPP_R			0x3
+#define GPD			0x4
 #define GPP_V			0x5
-#define GPD			0x6
-#define GPP_H			0x7
+#define GPP_H			0x6
+#define GPP_D			0x7
 #define GPP_U			0x8
 #define VGPIO			0x9
 #define GPP_F			0xA
 #define GPP_C			0xB
 #define GPP_E			0xC
 #define GPP_G			0xD
-#define GPP_S			0xE
 
 #define GPIO_NUM_GROUPS		15
 #define GPIO_MAX_NUM_PER_GROUP	32

src/soc/intel/elkhartlake/include/soc/pmc.h

@@ -105,19 +105,18 @@
 
 #define PMC_GPP_B				0x0
 #define PMC_GPP_T				0x1
-#define PMC_GPP_D				0x2
-#define PMC_GPP_A				0x3
-#define PMC_GPP_R				0x4
+#define PMC_GPP_A				0x2
+#define PMC_GPP_R				0x3
+#define PMC_GPD					0x4
 #define PMC_GPP_V				0x5
-#define PMC_GPD					0x6
-#define PMC_GPP_H				0x7
+#define PMC_GPP_H				0x6
+#define PMC_GPP_D				0x7
 #define PMC_GPP_U				0x8
 #define PMC_VGPIO				0x9
 #define PMC_GPP_F				0xA
 #define PMC_GPP_C				0xB
 #define PMC_GPP_E				0xC
 #define PMC_GPP_G				0xD
-#define PMC_GPP_S				0xE
 
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)