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FPGA based ADPLL Network in Verilog - Elec&Comp Eng Masters Project 2019

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Name		Name	Last commit message	Last commit date
Latest commit History 243 Commits
arduino/pwm		arduino/pwm
conf_paper		conf_paper
constraints		constraints
design_sources		design_sources
matlab		matlab
sim_sources		sim_sources
tex_files		tex_files
thesis		thesis
todo		todo
waveforms		waveforms
.gitattributes		.gitattributes
.gitignore		.gitignore
ADPLL_RTL_VIVADO.png		ADPLL_RTL_VIVADO.png
ADPLL_TEST_SETUP.png		ADPLL_TEST_SETUP.png
AGILENT_locking_4M7_to_5M0.png		AGILENT_locking_4M7_to_5M0.png
BB.pdf		BB.pdf
BB.svg		BB.svg
FIR_1.pdf		FIR_1.pdf
FIR_1.svg		FIR_1.svg
FIR_2.pdf		FIR_2.pdf
FIR_2.svg		FIR_2.svg
HMO_locking_4M7_to5M0.PNG		HMO_locking_4M7_to5M0.PNG
RO-wiki.png		RO-wiki.png
TIE.png		TIE.png
TIE_plot.png		TIE_plot.png
TM01.PNG		TM01.PNG
bad_waveform.png		bad_waveform.png
ccirc_2013_arch.PNG		ccirc_2013_arch.PNG
dist2.png		dist2.png
dist_2.png		dist_2.png
dist_adpll.png		dist_adpll.png
dist_adpll.svg		dist_adpll.svg
divider1.png		divider1.png
divider1.svg		divider1.svg
divider2.png		divider2.png
divider2.svg		divider2.svg
eldar_last_30_yrs.PNG		eldar_last_30_yrs.PNG
eldar_why_precise_clocking.PNG		eldar_why_precise_clocking.PNG
error_over_time_test.png		error_over_time_test.png
eugene.png		eugene.png
fixed_kp.png		fixed_kp.png
fixed_kp_zoom.png		fixed_kp_zoom.png
fpga_photo.png		fpga_photo.png
good_sim.png		good_sim.png
gutnik2000active.PNG		gutnik2000active.PNG
impl_locking.png		impl_locking.png
impl_locking_rect.png		impl_locking_rect.png
impl_waveform.png		impl_waveform.png
integer_lf.pdf		integer_lf.pdf
integer_lf.svg		integer_lf.svg
inverter_chain.dia		inverter_chain.dia
inverter_chain.png		inverter_chain.png
loop_filter.dia		loop_filter.dia
loop_filter.png		loop_filter.png
measurement_setup.jpg		measurement_setup.jpg
measurements		measurements
mizuno1998noise.PNG		mizuno1998noise.PNG
n4.png		n4.png
network.svg		network.svg
network_adpll.pdf		network_adpll.pdf
network_adpll.svg		network_adpll.svg
network_annotated.pdf		network_annotated.pdf
new_pdet1.pdf		new_pdet1.pdf
new_pdet1.svg		new_pdet1.svg
new_pdet2.pdf		new_pdet2.pdf
new_pdet2.svg		new_pdet2.svg
osc1.png		osc1.png
osc1.svg		osc1.svg
osc2.png		osc2.png
osc2.svg		osc2.svg
osc2_impl.pdf		osc2_impl.pdf
osc2_impl.svg		osc2_impl.svg
phase_accum.dia		phase_accum.dia
phase_accum.png		phase_accum.png
pi_simple.dia		pi_simple.dia
pi_simple.png		pi_simple.png
project.sublime-project		project.sublime-project
project.sublime-workspace		project.sublime-workspace
readme.md		readme.md
ring_osc.png		ring_osc.png
ro_new.pdf		ro_new.pdf
ro_new.svg		ro_new.svg
ro_rtl.dia		ro_rtl.dia
ro_rtl.png		ro_rtl.png
rtl.dia		rtl.dia
rtl.png		rtl.png
save_electronics_stuff.svg		save_electronics_stuff.svg
scope_0.png		scope_0.png
shan_bb_pd.PNG		shan_bb_pd.PNG
sim_locking.png		sim_locking.png
sim_locking_rect.png		sim_locking_rect.png
simple_pi.pdf		simple_pi.pdf
simple_pi.png		simple_pi.png
simple_pi.svg		simple_pi.svg
simple_sign_detection.pdf		simple_sign_detection.pdf
simple_sign_detection.svg		simple_sign_detection.svg
simple_tdc.pdf		simple_tdc.pdf
simple_tdc.svg		simple_tdc.svg
state_trans_diagram.dia		state_trans_diagram.dia
state_trans_diagram.png		state_trans_diagram.png