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As previously mentioned, the time-to-digital conversion is carried out by a tapped delay line. As with the \ac{RO}, inverters will be used to provide the delay between each tap, and thus the resolution of the \ac{TDL} and the length of each individual delay is based on the layout chosen by the router in Vivado. Due to this, the exact resolution of the phase detector is unknown, although the delay through inverters used in Vivado simulations, and the average delay computed based on \ac{RO} centre frequencies, can be used to estimate that of the phase detectors. Based these figures for the the propagation delay due to an inverter, $\tau_{inv}$ can be estimated to be in the region of $300~\si{\pico\second}$. As each tap consists of an inverter pair, the delay through the tap, $\tau_{tap} \approx 600~\si{\pico\second}$. Characterisation of the \ac{TDL}, through measurement of the delays steps in each \ac{TDL}, is technically possible, however, this is an time consuming process as many \acp{TDL} would need to be characterised in order to accurately compute the average delay.
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The delay line itself is shown in Figure \ref{fig:tdl_impl}, with each tap implemented by a pair of flip-flops and three inverters. For an $N$ bit width phase error detection, $2^{N-1}-1$ taps are required. In the case of this \ac{ADPLL}, a 5 bit two's complement error signal is required, thus the range of the signal is $[-16,15]\cap\mathbb{Z}$. If the range is made symmetrical, 15 taps are required to fill a signal of this size. From the diagram, it can be seen that unless edges are detected on each signal at exactly the same instant, it is almost impossible to measure a zero phase difference between reference and generated signals. This is an intentional decision, \cite{idkwhattocite}.
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The delay line itself is shown in Figure \ref{fig:tdl_impl}, with each tap implemented by a pair of flip-flops and three inverters. For an $N$ bit width phase error detection, $2^{N-1}-1$ taps are required. In the case of this \ac{ADPLL}, a 5 bit two's complement error signal is required, thus the range of the signal is $[-16,15]\cap\mathbb{Z}$. If the range is made symmetrical, 15 taps are required to fill a signal of this size. From the diagram, it can be seen that unless edges are detected on each signal at exactly the same instant, it is almost impossible to measure a zero phase difference between reference and generated signals. This is done to maximize the information carried by the digital signal \cite{shan2014phd}.
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