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cheri_extras.lem
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(*=======================================================================================*)
(* CHERI RISCV Sail Model *)
(* *)
(* This CHERI Sail RISC-V architecture model here, comprising all files and *)
(* directories except for the snapshots of the Lem and Sail libraries in the *)
(* prover_snapshots directory (which include copies of their licenses), is subject *)
(* to the BSD two-clause licence below. *)
(* *)
(* Copyright (c) 2017-2021 *)
(* Alasdair Armstrong *)
(* Thomas Bauereiss *)
(* Brian Campbell *)
(* Jessica Clarke *)
(* Nathaniel Wesley Filardo (contributions prior to July 2020, thereafter Microsoft) *)
(* Alexandre Joannou *)
(* Microsoft *)
(* Prashanth Mundkur *)
(* Robert Norton-Wright (contributions prior to March 2020, thereafter Microsoft) *)
(* Alexander Richardson *)
(* Peter Rugg *)
(* Peter Sewell *)
(* *)
(* All rights reserved. *)
(* *)
(* This software was developed by SRI International and the University of *)
(* Cambridge Computer Laboratory (Department of Computer Science and *)
(* Technology) under DARPA/AFRL contract FA8650-18-C-7809 ("CIFV"), and *)
(* under DARPA contract HR0011-18-C-0016 ("ECATS") as part of the DARPA *)
(* SSITH research programme. *)
(* *)
(* This software was developed within the Rigorous Engineering of *)
(* Mainstream Systems (REMS) project, partly funded by EPSRC grant *)
(* EP/K008528/1, at the Universities of Cambridge and Edinburgh. *)
(* *)
(* This project has received funding from the European Research Council *)
(* (ERC) under the European Union’s Horizon 2020 research and innovation *)
(* programme (grant agreement 789108, ELVER). *)
(* *)
(* Redistribution and use in source and binary forms, with or without *)
(* modification, are permitted provided that the following conditions *)
(* are met: *)
(* 1. Redistributions of source code must retain the above copyright *)
(* notice, this list of conditions and the following disclaimer. *)
(* 2. Redistributions in binary form must reproduce the above copyright *)
(* notice, this list of conditions and the following disclaimer in *)
(* the documentation and/or other materials provided with the *)
(* distribution. *)
(* *)
(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *)
(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *)
(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *)
(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *)
(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *)
(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *)
(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *)
(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *)
(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *)
(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *)
(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *)
(* SUCH DAMAGE. *)
(*=======================================================================================*)
open import Pervasives
open import Pervasives_extra
open import Sail2_instr_kinds
open import Sail2_values
open import Sail2_operators_mwords
open import Sail2_prompt_monad
open import Sail2_prompt
val write_ram : forall 'rv 'e 'n. Size 'n => write_kind -> mword ty64 -> integer -> mword 'n -> bool -> monad 'rv bool 'e
let write_ram wk addr width data tag =
write_memt wk addr width data (bitU_of_bool tag)
val read_ram : forall 'rv 'e 'n. Size 'n => read_kind -> mword ty64 -> integer -> bool -> monad 'rv (mword 'n * bool) 'e
let read_ram rk addr width read_tag =
if read_tag then
read_memt rk addr width >>= (fun ((data : mword 'n), (tag : bitU)) ->
bool_of_bitU_fail tag >>= (fun (tag : bool) ->
return (data, tag)))
else
read_mem rk () addr width >>= (fun (data : mword 'n) ->
return (data, false))
val write_tag_bool : forall 'rv 'e. mword ty64 -> bool -> monad 'rv unit 'e
let write_tag_bool addr tag =
read_memt Read_plain addr 16 >>= (fun ((cap : mword ty128), _) ->
write_memt Write_plain addr 16 cap (bitU_of_bool tag) >>= (fun _ -> return ()))
val read_tag_bool : forall 'rv 'e. mword ty64 -> monad 'rv bool 'e
let read_tag_bool addr =
read_memt Read_plain addr 16 >>= (fun ((cap : mword ty128), tag) ->
bool_of_bitU_fail tag)