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Milestone-3 | packets number fix
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‎Milestone-3/project_2_17.4/project_2.cache/wt/gui_handlers.wdf

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@ version:1
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10-
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11-
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12-
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10+
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12+
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15-
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:38:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3130:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f666c6f77:32:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f7274:31:00:00
@@ -38,19 +38,20 @@ version:1
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42-
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53+
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54+
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@@ -62,4 +63,4 @@ version:1
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65-
eof:2181121966
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eof:878370205

‎Milestone-3/project_2_17.4/project_2.cache/wt/java_command_handlers.wdf

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Original file line numberDiff line numberDiff line change
@@ -8,17 +8,17 @@ version:1
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11-
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11+
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eof:934516939
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eof:1473307307

‎Milestone-3/project_2_17.4/project_2.cache/wt/project.wpc

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@@ -1,3 +1,3 @@
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version:1
2-
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eof:

‎Milestone-3/project_2_17.4/project_2.cache/wt/webtalk_pa.xml

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Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
<!--The data in this file is primarily intended for consumption by Xilinx tools.
44
The structure and the elements are likely to change over the next few releases.
55
This means code written to parse this file will need to be revisited each subsequent release.-->
6-
<application name="pa" timeStamp="Fri May 31 14:50:02 2019">
6+
<application name="pa" timeStamp="Fri May 31 15:37:21 2019">
77
<section name="Project Information" visible="false">
88
<property name="ProjectID" value="9f792e26a1104d8fb771d610c00cee58" type="ProjectID"/>
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<property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -26,19 +26,19 @@ This means code written to parse this file will need to be revisited each subseq
2626
<property name="IPPackagerHandler" value="3" type="JavaHandler"/>
2727
<property name="IPPackagerWizardHandler" value="1" type="JavaHandler"/>
2828
<property name="OpenBlockDesign" value="2" type="JavaHandler"/>
29-
<property name="OpenProject" value="3" type="JavaHandler"/>
29+
<property name="OpenProject" value="4" type="JavaHandler"/>
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<property name="ReportIPStatus" value="1" type="JavaHandler"/>
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<property name="SaveFileProxyHandler" value="3" type="JavaHandler"/>
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<property name="SaveRSBDesign" value="1" type="JavaHandler"/>
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<property name="SetTopNode" value="1" type="JavaHandler"/>
34-
<property name="SimulationRelaunch" value="6" type="JavaHandler"/>
35-
<property name="SimulationRun" value="8" type="JavaHandler"/>
36-
<property name="SimulationRunForTime" value="6" type="JavaHandler"/>
34+
<property name="SimulationRelaunch" value="7" type="JavaHandler"/>
35+
<property name="SimulationRun" value="9" type="JavaHandler"/>
36+
<property name="SimulationRunForTime" value="8" type="JavaHandler"/>
3737
<property name="ToggleViewNavigator" value="1" type="JavaHandler"/>
3838
<property name="UpgradeIP" value="4" type="JavaHandler"/>
3939
<property name="ValidateRSBDesign" value="1" type="JavaHandler"/>
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<property name="ViewTaskSimulation" value="1" type="JavaHandler"/>
41-
<property name="WaveformOpenConfiguration" value="4" type="JavaHandler"/>
41+
<property name="WaveformOpenConfiguration" value="5" type="JavaHandler"/>
4242
</item>
4343
<item name="Gui Handlers">
4444
<property name="AbstractFileView_CLOSE" value="1" type="GuiHandlerData"/>
@@ -49,12 +49,12 @@ This means code written to parse this file will need to be revisited each subseq
4949
<property name="CoreAndInterfacesBaseTreeTablePanel_REFRESH_ALL_REPOSITORIES" value="1" type="GuiHandlerData"/>
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<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="11" type="GuiHandlerData"/>
5151
<property name="CoreTreeTablePanel_DELETE_IP" value="1" type="GuiHandlerData"/>
52-
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="42" type="GuiHandlerData"/>
53-
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="18" type="GuiHandlerData"/>
54-
<property name="GettingStartedView_OPEN_PROJECT" value="3" type="GuiHandlerData"/>
52+
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="45" type="GuiHandlerData"/>
53+
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="20" type="GuiHandlerData"/>
54+
<property name="GettingStartedView_OPEN_PROJECT" value="4" type="GuiHandlerData"/>
5555
<property name="IPStatusSectionPanel_UPGRADE_SELECTED" value="4" type="GuiHandlerData"/>
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<property name="IdentificationContentPanel_VERSION" value="5" type="GuiHandlerData"/>
57-
<property name="MainMenuMgr_FILE" value="8" type="GuiHandlerData"/>
57+
<property name="MainMenuMgr_FILE" value="10" type="GuiHandlerData"/>
5858
<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
5959
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="1" type="GuiHandlerData"/>
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<property name="MainMenuMgr_REPORT" value="1" type="GuiHandlerData"/>
@@ -80,19 +80,20 @@ This means code written to parse this file will need to be revisited each subseq
8080
<property name="PACommandNames_IP_PACKAGER_WIZARD" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_SAVE_RSB_DESIGN" value="1" type="GuiHandlerData"/>
8282
<property name="PACommandNames_SET_AS_TOP" value="1" type="GuiHandlerData"/>
83-
<property name="PACommandNames_SIMULATION_LIVE_RUN" value="6" type="GuiHandlerData"/>
84-
<property name="PACommandNames_SIMULATION_RELAUNCH" value="6" type="GuiHandlerData"/>
83+
<property name="PACommandNames_SIMULATION_LIVE_RUN" value="8" type="GuiHandlerData"/>
84+
<property name="PACommandNames_SIMULATION_RELAUNCH" value="7" type="GuiHandlerData"/>
8585
<property name="PACommandNames_SIMULATION_RESET_BEHAVIORAL" value="2" type="GuiHandlerData"/>
86-
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="6" type="GuiHandlerData"/>
86+
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="7" type="GuiHandlerData"/>
8787
<property name="PACommandNames_TOGGLE_VIEW_NAV" value="1" type="GuiHandlerData"/>
8888
<property name="PACommandNames_VALIDATE_RSB_DESIGN" value="1" type="GuiHandlerData"/>
8989
<property name="PAViews_CODE" value="1" type="GuiHandlerData"/>
9090
<property name="PackagerStepsPanel_PACKAGER_STEPS_LIST" value="28" type="GuiHandlerData"/>
9191
<property name="PlanAheadTab_REFRESH_IP_CATALOG" value="3" type="GuiHandlerData"/>
92+
<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="1" type="GuiHandlerData"/>
9293
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
9394
<property name="QuickHelp_HELP" value="1" type="GuiHandlerData"/>
94-
<property name="RDICommands_WAVEFORM_OPEN_CONFIGURATION" value="4" type="GuiHandlerData"/>
95-
<property name="RDIViews_WAVEFORM_VIEWER" value="37" type="GuiHandlerData"/>
95+
<property name="RDICommands_WAVEFORM_OPEN_CONFIGURATION" value="5" type="GuiHandlerData"/>
96+
<property name="RDIViews_WAVEFORM_VIEWER" value="39" type="GuiHandlerData"/>
9697
<property name="ReviewContentPanel_PACKAGE_IP" value="5" type="GuiHandlerData"/>
9798
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="4" type="GuiHandlerData"/>
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<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="4" type="GuiHandlerData"/>
@@ -106,9 +107,9 @@ This means code written to parse this file will need to be revisited each subseq
106107
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="12" type="GuiHandlerData"/>
107108
</item>
108109
<item name="Other">
109-
<property name="GuiMode" value="45" type="GuiMode"/>
110+
<property name="GuiMode" value="47" type="GuiMode"/>
110111
<property name="BatchMode" value="0" type="BatchMode"/>
111-
<property name="TclMode" value="40" type="TclMode"/>
112+
<property name="TclMode" value="42" type="TclMode"/>
112113
</item>
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</section>
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</application>

‎Milestone-3/project_2_17.4/project_2.sim/sim_1/behav/xsim/compile.bat

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Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ REM Filename : compile.bat
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REM Simulator : Xilinx Vivado Simulator
77
REM Description : Script for compiling the simulation design source files
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REM
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REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

‎Milestone-3/project_2_17.4/project_2.sim/sim_1/behav/xsim/elaborate.bat

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REM Simulator : Xilinx Vivado Simulator
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REM Description : Script for elaborating the compiled design
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REM
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‎Milestone-3/project_2_17.4/project_2.sim/sim_1/behav/xsim/elaborate.log

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Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto 9e2ce5b03cf34386aea9708b249be066 --incr --debug typical --relax --mt 2 -L axi_infrastructure_v1_1_0 -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L axi_vip_v1_1_1 -L processing_system7_vip_v1_0_3 -L xil_defaultlib -L blk_mem_gen_v8_4_1 -L blk_mem_gen_v8_3_6 -L axi_bram_ctrl_v4_0_13 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_12 -L lib_pkg_v1_0_2 -L fifo_generator_v13_2_1 -L lib_fifo_v1_0_10 -L lib_srl_fifo_v1_0_2 -L axi_datamover_v5_1_17 -L axi_sg_v4_1_8 -L axi_dma_v7_1_16 -L xlconcat_v2_1_1 -L generic_baseblocks_v2_1_0 -L axi_register_slice_v2_1_15 -L axi_data_fifo_v2_1_14 -L axi_crossbar_v2_1_16 -L axi_protocol_converter_v2_1_15 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_behav xil_defaultlib.tb xil_defaultlib.glbl -log elaborate.log -cc gcc
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Using 2 slave threads.
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Starting static elaboration
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WARNING: [VRFC 10-278] actual bit length 2 differs from formal bit length 16 for port IRQ_F2P [C:/Users/CS/Desktop/Vivado-Projects/Milestone_3_again/project_2_17.4/project_2.ip_user_files/bd/base_zynq/ip/base_zynq_processing_system7_0_0/sim/base_zynq_processing_system7_0_0.v:587]
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WARNING: [VRFC 10-278] actual bit length 2 differs from formal bit length 16 for port IRQ_F2P [C:/Users/CS/Desktop/Vivado-Projects/Milestone_3_check/project_2_17.4/project_2.ip_user_files/bd/base_zynq/ip/base_zynq_processing_system7_0_0/sim/base_zynq_processing_system7_0_0.v:587]
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WARNING: [VRFC 10-278] actual bit length 12 differs from formal bit length 6 for port m_axi_bid [/wrk/2017.4/nightly/2017_12_15_2086221/packages/customer/vivado/data/ip/xilinx/processing_system7_vip_v1_0/hdl/processing_system7_vip_v1_0_vl_rfs.sv:4598]
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WARNING: [VRFC 10-278] actual bit length 12 differs from formal bit length 6 for port m_axi_rid [/wrk/2017.4/nightly/2017_12_15_2086221/packages/customer/vivado/data/ip/xilinx/processing_system7_vip_v1_0/hdl/processing_system7_vip_v1_0_vl_rfs.sv:4616]
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WARNING: [VRFC 10-278] actual bit length 12 differs from formal bit length 6 for port m_axi_bid [/wrk/2017.4/nightly/2017_12_15_2086221/packages/customer/vivado/data/ip/xilinx/processing_system7_vip_v1_0/hdl/processing_system7_vip_v1_0_vl_rfs.sv:6554]

‎Milestone-3/project_2_17.4/project_2.sim/sim_1/behav/xsim/simulate.bat

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REM Simulator : Xilinx Vivado Simulator
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REM Description : Script for simulating the design by launching the simulator
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REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

‎Milestone-3/project_2_17.4/project_2.sim/sim_1/behav/xsim/tb_behav.wdb

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‎Milestone-3/project_2_17.4/project_2.sim/sim_1/behav/xsim/xelab.pb

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