This repository was archived by the owner on Oct 14, 2020. It is now read-only.
File tree
1,448 files changed
+5224117
-0
lines changed- Milestone-1/Reference-project/project_2_17.4
- ip_repo
- edit_myip_v1_1.cache/wt
- edit_myip_v1_1.hw
- my_ip_hls
- .apc
- .settings
- solution1
- .autopilot
- db
- impl
- ip
- bd
- constraints
- doc
- example
- hdl
- verilog
- vhdl
- misc
- xgui
- misc
- verilog
- project.cache/wt
- project.hw
- vhdl
- project.cache/wt
- project.hw
- syn
- report
- systemc
- verilog
- vhdl
- myip_1.1
- bd
- hdl
- xgui
- project_2.cache/wt
- project_2.hw
- project_2.ip_user_files
- bd/base_zynq
- ip
- base_zynq_auto_pc_0/sim
- base_zynq_auto_pc_1/sim
- base_zynq_axi_bram_ctrl_0_0/sim
- base_zynq_axi_bram_ctrl_0_1/sim
- base_zynq_axi_dma_0_0/sim
- base_zynq_blk_mem_gen_0_0/sim
- base_zynq_myip_0_0/sim
- base_zynq_processing_system7_0_0/sim
- base_zynq_rst_ps7_0_50M_0/sim
- base_zynq_xbar_0/sim
- base_zynq_xbar_1/sim
- base_zynq_xlconcat_0_0/sim
- sim
- mem_init_files
- sim_scripts/base_zynq
- activehdl
- ies
- modelsim
- questa
- riviera
- vcs
- xsim
- project_2.sim/sim_1/behav
- xsim.dir
- tb_behav
- webtalk
- xil_defaultlib
- xsim
- xsim.dir
- tb_behav
- obj
- webtalk
- xil_defaultlib
- project_2.srcs
- sim_1/imports/base_zynq
- sources_1/bd/base_zynq
- hdl
- hw_handoff
- ip
- base_zynq_auto_pc_0
- sim
- base_zynq_auto_pc_1
- sim
- base_zynq_axi_bram_ctrl_0_0
- sim
- base_zynq_axi_bram_ctrl_0_1
- sim
- base_zynq_axi_dma_0_0
- sim
- base_zynq_axi_interconnect_0_0
- base_zynq_blk_mem_gen_0_0
- sim
- base_zynq_myip_0_0
- sim
- base_zynq_processing_system7_0_0
- sim
- base_zynq_ps7_0_axi_periph_0
- base_zynq_rst_ps7_0_50M_0
- sim
- base_zynq_xbar_0
- sim
- base_zynq_xbar_1
- sim
- base_zynq_xlconcat_0_0
- sim
- sim
- synth
- ui
- project_2.tmp/myip_v1_2_project
- myip_v1_2_project.cache/wt
- myip_v1_2_project.hw
- Milestone-3/project_2_17.4
- ip_repo
- edit_myip_v1_1.cache/wt
- edit_myip_v1_1.hw
- my_ip_hls
- .apc
- .settings
- solution1
- .autopilot
- db
- driver
- data
- src
- csim
- build
- obj
- report
- impl
- ip
- bd
- constraints
- doc
- drivers/my_ip_hls_v1_1
- data
- src
- example
- hdl
- verilog
- vhdl
- misc
- xgui
- misc
- drivers/my_ip_hls_v1_1
- data
- src
- verilog
- project.cache/wt
- project.hw
- vhdl
- project.cache/wt
- project.hw
- syn
- report
- systemc
- verilog
- vhdl
- myip_1.1
- bd
- hdl
- xgui
- project_2.cache/wt
- project_2.hw
- project_2.ip_user_files
- bd/base_zynq
- ip
- base_zynq_auto_pc_0/sim
- base_zynq_auto_pc_1/sim
- base_zynq_auto_pc_2/sim
- base_zynq_axi_bram_ctrl_0_0/sim
- base_zynq_axi_bram_ctrl_0_1/sim
- base_zynq_axi_dma_0_0/sim
- base_zynq_blk_mem_gen_0_0/sim
- base_zynq_my_ip_hls_0_0/sim
- base_zynq_processing_system7_0_0/sim
- base_zynq_rst_ps7_0_50M_0/sim
- base_zynq_xbar_0/sim
- base_zynq_xbar_1/sim
- base_zynq_xlconcat_0_0/sim
- sim
- mem_init_files
- sim_scripts/base_zynq
- activehdl
- ies
- modelsim
- questa
- riviera
- vcs
- xsim
- project_2.sim/sim_1/behav
- xsim.dir
- tb_behav
- webtalk
- xil_defaultlib
- xsim
- xsim.dir
- tb_behav
- obj
- webtalk
- xil_defaultlib
- project_2.srcs
- sim_1/imports/base_zynq
- sources_1/bd/base_zynq
- hdl
- hw_handoff
- ip
- base_zynq_auto_pc_0
- sim
- base_zynq_auto_pc_1
- sim
- base_zynq_auto_pc_2
- sim
- base_zynq_axi_bram_ctrl_0_0
- sim
- base_zynq_axi_bram_ctrl_0_1
- sim
- base_zynq_axi_dma_0_0
- sim
- base_zynq_axi_interconnect_0_0
- base_zynq_blk_mem_gen_0_0
- sim
- base_zynq_my_ip_hls_0_0
- sim
- base_zynq_processing_system7_0_0
- sim
- base_zynq_ps7_0_axi_periph_0
- base_zynq_rst_ps7_0_50M_0
- sim
- base_zynq_xbar_0
- sim
- base_zynq_xbar_1
- sim
- base_zynq_xlconcat_0_0
- sim
- sim
- synth
- ui
- project_2.tmp/myip_v1_2_project
- myip_v1_2_project.cache/wt
- myip_v1_2_project.hw
Some content is hidden
Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.
1,448 files changed
+5224117
-0
lines changedLines changed: 40 additions & 0 deletions
Original file line number | Diff line number | Diff line change | |
---|---|---|---|
| |||
| 1 | + | |
| 2 | + | |
| 3 | + | |
| 4 | + | |
| 5 | + | |
| 6 | + | |
| 7 | + | |
| 8 | + | |
| 9 | + | |
| 10 | + | |
| 11 | + | |
| 12 | + | |
| 13 | + | |
| 14 | + | |
| 15 | + | |
| 16 | + | |
| 17 | + | |
| 18 | + | |
| 19 | + | |
| 20 | + | |
| 21 | + | |
| 22 | + | |
| 23 | + | |
| 24 | + | |
| 25 | + | |
| 26 | + | |
| 27 | + | |
| 28 | + | |
| 29 | + | |
| 30 | + | |
| 31 | + | |
| 32 | + | |
| 33 | + | |
| 34 | + | |
| 35 | + | |
| 36 | + | |
| 37 | + | |
| 38 | + | |
| 39 | + | |
| 40 | + |
Lines changed: 15 additions & 0 deletions
Original file line number | Diff line number | Diff line change | |
---|---|---|---|
| |||
| 1 | + | |
| 2 | + | |
| 3 | + | |
| 4 | + | |
| 5 | + | |
| 6 | + | |
| 7 | + | |
| 8 | + | |
| 9 | + | |
| 10 | + | |
| 11 | + | |
| 12 | + | |
| 13 | + | |
| 14 | + | |
| 15 | + |
Lines changed: 3 additions & 0 deletions
Original file line number | Diff line number | Diff line change | |
---|---|---|---|
| |||
| 1 | + | |
| 2 | + | |
| 3 | + |
Lines changed: 81 additions & 0 deletions
Original file line number | Diff line number | Diff line change | |
---|---|---|---|
| |||
| 1 | + | |
| 2 | + | |
| 3 | + | |
| 4 | + | |
| 5 | + | |
| 6 | + | |
| 7 | + | |
| 8 | + | |
| 9 | + | |
| 10 | + | |
| 11 | + | |
| 12 | + | |
| 13 | + | |
| 14 | + | |
| 15 | + | |
| 16 | + | |
| 17 | + | |
| 18 | + | |
| 19 | + | |
| 20 | + | |
| 21 | + | |
| 22 | + | |
| 23 | + | |
| 24 | + | |
| 25 | + | |
| 26 | + | |
| 27 | + | |
| 28 | + | |
| 29 | + | |
| 30 | + | |
| 31 | + | |
| 32 | + | |
| 33 | + | |
| 34 | + | |
| 35 | + | |
| 36 | + | |
| 37 | + | |
| 38 | + | |
| 39 | + | |
| 40 | + | |
| 41 | + | |
| 42 | + | |
| 43 | + | |
| 44 | + | |
| 45 | + | |
| 46 | + | |
| 47 | + | |
| 48 | + | |
| 49 | + | |
| 50 | + | |
| 51 | + | |
| 52 | + | |
| 53 | + | |
| 54 | + | |
| 55 | + | |
| 56 | + | |
| 57 | + | |
| 58 | + | |
| 59 | + | |
| 60 | + | |
| 61 | + | |
| 62 | + | |
| 63 | + | |
| 64 | + | |
| 65 | + | |
| 66 | + | |
| 67 | + | |
| 68 | + | |
| 69 | + | |
| 70 | + | |
| 71 | + | |
| 72 | + | |
| 73 | + | |
| 74 | + | |
| 75 | + | |
| 76 | + | |
| 77 | + | |
| 78 | + | |
| 79 | + | |
| 80 | + | |
| 81 | + |
Lines changed: 6 additions & 0 deletions
Original file line number | Diff line number | Diff line change | |
---|---|---|---|
| |||
| 1 | + | |
| 2 | + | |
| 3 | + | |
| 4 | + | |
| 5 | + | |
| 6 | + |
0 commit comments