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21 changes: 21 additions & 0 deletions
21
...tom/snapshots/hugr_llvm__custom__prelude__test__prelude_const_external_symbol@llvm14.snap
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--- | ||
source: src/custom/prelude.rs | ||
expression: module.to_string() | ||
--- | ||
; ModuleID = 'test_context' | ||
source_filename = "test_context" | ||
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@sym2 = external global { i32, { i64, { i32, {}, {}, {} } }, {} } | ||
@sym1 = external constant i64 | ||
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define { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } @_hl.main.1() { | ||
alloca_block: | ||
br label %entry_block | ||
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entry_block: ; preds = %alloca_block | ||
%sym2 = load { i32, { i64, { i32, {}, {}, {} } }, {} }, { i32, { i64, { i32, {}, {}, {} } }, {} }* @sym2, align 4 | ||
%sym1 = load i64, i64* @sym1, align 4 | ||
%mrv = insertvalue { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } undef, i64 %sym1, 0 | ||
%mrv5 = insertvalue { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } %mrv, { i32, { i64, { i32, {}, {}, {} } }, {} } %sym2, 1 | ||
ret { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } %mrv5 | ||
} |
33 changes: 33 additions & 0 deletions
33
...s/hugr_llvm__custom__prelude__test__prelude_const_external_symbol@pre-mem2reg@llvm14.snap
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,33 @@ | ||
--- | ||
source: src/custom/prelude.rs | ||
expression: module.to_string() | ||
--- | ||
; ModuleID = 'test_context' | ||
source_filename = "test_context" | ||
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@sym2 = external global { i32, { i64, { i32, {}, {}, {} } }, {} } | ||
@sym1 = external constant i64 | ||
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define { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } @_hl.main.1() { | ||
alloca_block: | ||
%"0" = alloca i64, align 8 | ||
%"1" = alloca { i32, { i64, { i32, {}, {}, {} } }, {} }, align 8 | ||
%"7_0" = alloca { i32, { i64, { i32, {}, {}, {} } }, {} }, align 8 | ||
%"5_0" = alloca i64, align 8 | ||
br label %entry_block | ||
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entry_block: ; preds = %alloca_block | ||
%sym2 = load { i32, { i64, { i32, {}, {}, {} } }, {} }, { i32, { i64, { i32, {}, {}, {} } }, {} }* @sym2, align 4 | ||
store { i32, { i64, { i32, {}, {}, {} } }, {} } %sym2, { i32, { i64, { i32, {}, {}, {} } }, {} }* %"7_0", align 4 | ||
%sym1 = load i64, i64* @sym1, align 4 | ||
store i64 %sym1, i64* %"5_0", align 4 | ||
%"5_01" = load i64, i64* %"5_0", align 4 | ||
%"7_02" = load { i32, { i64, { i32, {}, {}, {} } }, {} }, { i32, { i64, { i32, {}, {}, {} } }, {} }* %"7_0", align 4 | ||
store i64 %"5_01", i64* %"0", align 4 | ||
store { i32, { i64, { i32, {}, {}, {} } }, {} } %"7_02", { i32, { i64, { i32, {}, {}, {} } }, {} }* %"1", align 4 | ||
%"03" = load i64, i64* %"0", align 4 | ||
%"14" = load { i32, { i64, { i32, {}, {}, {} } }, {} }, { i32, { i64, { i32, {}, {}, {} } }, {} }* %"1", align 4 | ||
%mrv = insertvalue { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } undef, i64 %"03", 0 | ||
%mrv5 = insertvalue { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } %mrv, { i32, { i64, { i32, {}, {}, {} } }, {} } %"14", 1 | ||
ret { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } %mrv5 | ||
} |
14 changes: 14 additions & 0 deletions
14
src/custom/snapshots/hugr_llvm__custom__prelude__test__prelude_const_usize@llvm14.snap
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@@ -0,0 +1,14 @@ | ||
--- | ||
source: src/custom/prelude.rs | ||
expression: module.to_string() | ||
--- | ||
; ModuleID = 'test_context' | ||
source_filename = "test_context" | ||
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define i64 @_hl.main.1() { | ||
alloca_block: | ||
br label %entry_block | ||
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entry_block: ; preds = %alloca_block | ||
ret i64 17 | ||
} |
20 changes: 20 additions & 0 deletions
20
...m/snapshots/hugr_llvm__custom__prelude__test__prelude_const_usize@pre-mem2reg@llvm14.snap
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,20 @@ | ||
--- | ||
source: src/custom/prelude.rs | ||
expression: module.to_string() | ||
--- | ||
; ModuleID = 'test_context' | ||
source_filename = "test_context" | ||
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define i64 @_hl.main.1() { | ||
alloca_block: | ||
%"0" = alloca i64, align 8 | ||
%"5_0" = alloca i64, align 8 | ||
br label %entry_block | ||
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entry_block: ; preds = %alloca_block | ||
store i64 17, i64* %"5_0", align 4 | ||
%"5_01" = load i64, i64* %"5_0", align 4 | ||
store i64 %"5_01", i64* %"0", align 4 | ||
%"02" = load i64, i64* %"0", align 4 | ||
ret i64 %"02" | ||
} |
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