optimize llmulu_b and fix clock cycle count for lmulu_b

Author: ZERICO2005

src/crt/llmulu_b.src

@@ -1,68 +1,75 @@
 	assume	adl=1
 
 	section	.text
+
 	public	__llmulu_b
+
 __llmulu_b:
-	push	af
+; Multiplies BC:UDE:UHL by (SP) and returns the 64-bit unsigned product bc:ude:uhl.
+;    I: (SP) = 8-bit multiplier, BC:UDE:UHL = multiplicand, ADL=1
+;    O: bc:ude:uhl = BC:UDE:UHL * (SP)
+;   CC: 101*r(PC)+21*r(SPL)+18*w(SPL)+33
+;   CC: 100 bytes | 101F + 21R + 18W + 33
 	push	iy
 	ld	iy, 0
 	add	iy, sp
 	push	de
 	push	hl
-	ld	a, (iy + 9)
-	ld	h, a
+	push	bc
+	ld	b, (iy + 6)
+	ld	c, 0
+	ld	h, b
 	mlt	hl
 	ld	(iy - 6), l
-	ld	d, a
+	ld	d, b
 	ld	e, (iy - 5)
 	mlt	de
 	ld	l, h
-	ld	h, 0
+	ld	h, c
 	add	hl, de
 	ld	(iy - 5), l
-	ld	d, a
+	ld	d, b
 	ld	e, (iy - 4)
 	mlt	de
 	ld	l, h
-	ld	h, 0
+	ld	h, c
 	add	hl, de
 	ld	(iy - 4), l
-	ld	d, a
+	ld	d, b
 	ld	e, (iy - 3)
 	mlt	de
 	ld	l, h
-	ld	h, 0
+	ld	h, c
 	add	hl, de
 	ld	(iy - 3), l
-	ld	d, a
+	ld	d, b
 	ld	e, (iy - 2)
 	mlt	de
 	ld	l, h
-	ld	h, 0
+	ld	h, c
 	add	hl, de
 	ld	(iy - 2), l
-	ld	d, a
+	ld	d, b
 	ld	e, (iy - 1)
 	mlt	de
 	ld	l, h
-	ld	h, 0
+	ld	h, c
 	add	hl, de
 	ld	(iy - 1), l
-	ld	d, a
-	ld	e, c
-	mlt	de
+
+	pop	de
 	ld	l, h
-	ld	h, 0
+	ld	c, d
+	ld	d, b
+	mlt	bc
+	ld	h, c
+	mlt	de
+
 	add	hl, de
+	ld	b, h
 	ld	c, l
-	ld	d, a
-	ld	e, b
-	mlt	de
-	ld	a, h
-	add	a, e
-	ld	b, a
+
 	pop	hl
 	pop	de
 	pop	iy
-	pop	af
 	ret

src/crt/lmulu_b.src

@@ -9,8 +9,8 @@ __lmulu_b:
 ; Multiplies EUHL by A and returns the 32-bit product euhl.
 ;    I: A=multiplier, EUHL=multiplicand, ADL=1
 ;    O: euhl=EUHL*A
-;   CC: 43*r(PC)+12*r(SPL)+9*w(SPL)+13
-;   CC: 42 bytes | 43F + 12R + 9W + 13
+;   CC: 43*r(PC)+12*r(SPL)+9*w(SPL)+17
+;   CC: 42 bytes | 43F + 12R + 9W + 17
 Mul_EUHL_A_EUHL:
 	push	bc
 	push	de
@@ -45,7 +45,7 @@ Mul_EUHL_A_EUHL:
 	add	hl, hl
 	add	hl, hl
 	add	hl, hl
-	
+
 	mlt	de	; DE = A * L
 	add	hl, de	; UHL = AH.hi + AU.lo, AH.lo + AL.hi, AL.lo
 

src/crt/lmulu_b_fast.src

@@ -9,8 +9,8 @@ __lmulu_b_fast:
 ; Multiplies EUHL by A and returns the 32-bit product euhl.
 ;    I: A=multiplier, EUHL=multiplicand, ADL=1
 ;    O: euhl=EUHL*A
-;   CC: 37*r(PC)+6*r(SPL)+3*w(SPL)+13
-;   CC: 36 bytes | 37F + 6R + 3W + 13
+;   CC: 37*r(PC)+6*r(SPL)+3*w(SPL)+17
+;   CC: 36 bytes | 37F + 6R + 3W + 17
 Mul_EUHL_A_EUHL:
 	dec	sp
 	push	hl
@@ -42,7 +42,7 @@ Mul_EUHL_A_EUHL:
 	add	hl, hl
 	add	hl, hl
 	add	hl, hl
-	
+
 	mlt	de	; DE = A * L
 	add	hl, de	; UHL = AH.hi + AU.lo, AH.lo + AL.hi, AL.lo
 

test/standalone/mulu_b/src/crt_wrap.asm

@@ -90,11 +90,26 @@ _CRT_lmulu_b_fast:
 	ld	a, (iy + 9)
 	jp	__lmulu_b_fast
 
+	public	_CRT_llmulu_b
+_CRT_llmulu_b:
+	ld	iy, 0
+	add	iy, sp
+	ld	l, (iy + 12)
+	push	hl
+	ld	hl, (iy + 3)
+	ld	de, (iy + 6)
+	ld	bc, (iy + 9)
+	call	__llmulu_b
+	ld	sp, iy
+	ret
+
 	extern	__smulu_b
 	extern	__smulu_b_fast
-	
+
 	extern	__imulu_b
 	extern	__imulu_b_fast
 
 	extern	__lmulu_b
 	extern	__lmulu_b_fast
+
+	extern	__llmulu_b

test/standalone/mulu_b/src/main.c

@@ -113,6 +113,8 @@ uint24_t CRT_imulu_b_fast(uint24_t, uint8_t);
 uint32_t CRT_lmulu_b(uint32_t, uint8_t);
 uint32_t CRT_lmulu_b_fast(uint32_t, uint8_t);
 
+uint64_t CRT_llmulu_b(uint64_t, uint8_t);
+
 typedef struct reg_group {
     union {
         struct {
@@ -177,6 +179,14 @@ static bool test_A_UBC_UD(void) {
     return false;
 }
 
+static bool test_A(void) {
+    if (prev_reg.A == next_reg.A) {
+        return true;
+    }
+    print_reg();
+    return false;
+}
+
 int test_smulu_b(void) {
     for (int i = 0; i < RANDOM_TEST_COUNT; i++) {
         uint16_t truth, guess, x;
@@ -258,6 +268,20 @@ int test_lmulu_b_fast(void) {
     return 0;
 }
 
+int test_llmulu_b(void) {
+    for (int i = 0; i < RANDOM_TEST_COUNT; i++) {
+        uint64_t truth, guess, x;
+        uint8_t y;
+        x = rand64();
+        y = rand8();
+        truth = x * (uint64_t)y;
+        guess = CRT_llmulu_b(x, y);
+        CMP("%016llX", x, y, truth, guess);
+        C((test_A()));
+    }
+    return 0;
+}
+
 int run_tests(void) {
     srand(AUTOTEST_SEED);
     int ret = 0;
@@ -267,6 +291,7 @@ int run_tests(void) {
     TEST(test_imulu_b_fast());
     TEST(test_lmulu_b());
     TEST(test_lmulu_b_fast());
+    TEST(test_llmulu_b());
 
     return ret;
 }