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core: make the TI-82AEP use pre-A rev.
1 parent c334cdc commit f81119c

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2 files changed

+18
-12
lines changed

2 files changed

+18
-12
lines changed

core/asic.c

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -104,8 +104,8 @@ static asic_rev_t report_reset(asic_rev_t loaded_rev, emu_device_t device, bool*
104104
}
105105
}
106106

107-
/* By default, ignore Python Edition in certificate if boot code is too old */
108-
if (loaded_rev == ASIC_REV_AUTO && default_rev < ASIC_REV_M) {
107+
/* By default, ignore Python Edition in certificate if boot code is too old, unless 82AEP */
108+
if (loaded_rev == ASIC_REV_AUTO && default_rev < ASIC_REV_M && device != TI82AEP) {
109109
*python = false;
110110
}
111111
}
@@ -121,9 +121,15 @@ static asic_rev_t report_reset(asic_rev_t loaded_rev, emu_device_t device, bool*
121121
}
122122

123123
static void set_features() {
124-
asic.im2 = (asic.revision < ASIC_REV_I);
125-
asic.serFlash = (asic.revision >= ASIC_REV_M);
126-
asic.hasWorkingSPIReads = (asic.device == TI82AEP);
124+
if (asic.device == TI82AEP) {
125+
asic.im2 = false;
126+
asic.serFlash = true;
127+
asic.hasWorkingSPIReads = true;
128+
} else { /* 83/84 CE */
129+
asic.im2 = (asic.revision < ASIC_REV_I);
130+
asic.serFlash = (asic.revision >= ASIC_REV_M);
131+
asic.hasWorkingSPIReads = false;
132+
}
127133
}
128134

129135
void asic_init(void) {

core/bootver.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,18 @@
11
#include "bootver.h"
22

3-
static const boot_ver_t minRevA_CE = { 5, 0, 0, 0 }; /* Rev A */
3+
static const boot_ver_t minRev0_CE = { 5, 0, 0, 0 }; /* Rev pre-A */
44
static const boot_ver_t minRevI_CE = { 5, 0, 0, 0 }; /* Rev I */
55
static const boot_ver_t minRevM_CE = { 5, 3, 6, 0 }; /* Rev M */
6-
static const boot_ver_t minRevM_82 = { 5, 6, 3, 0 }; /* Rev pre-A of 82AEP, but otherwise the same JB-007 ASIC as M on CE */
7-
static const boot_ver_t maxRevA_CE = { 5, 3, 5, 65535 }; /* Rev A */
6+
static const boot_ver_t minRev0_82 = { 5, 6, 3, 0 }; /* Rev pre-A of 82AEP, but otherwise the same JB-007 ASIC as M on CE */
7+
static const boot_ver_t maxRev0_CE = { 5, 3, 5, 65535 }; /* Rev pre-A */
88
static const boot_ver_t maxRevI_CE = { 5, 3, 5, 65535 }; /* Rev I */
99
static const boot_ver_t maxRev = { 255, 255, 255, 65535 }; /* Rev M */
1010

1111
/* NULL means unsupported */
12-
static const boot_ver_t* asic_min_ver_8384CE[] = { &minRevA_CE, &minRevI_CE, &minRevM_CE };
13-
static const boot_ver_t* asic_max_ver_8384CE[] = { &maxRevA_CE, &maxRevI_CE, &maxRev };
14-
static const boot_ver_t* asic_min_ver_82AEP[] = { NULL, NULL, &minRevM_82 };
15-
static const boot_ver_t* asic_max_ver_82AEP[] = { NULL, NULL, &maxRev };
12+
static const boot_ver_t* asic_min_ver_8384CE[] = { &minRev0_CE, &minRevI_CE, &minRevM_CE };
13+
static const boot_ver_t* asic_max_ver_8384CE[] = { &maxRev0_CE, &maxRevI_CE, &maxRev };
14+
static const boot_ver_t* asic_min_ver_82AEP[] = { &minRev0_82, NULL, NULL };
15+
static const boot_ver_t* asic_max_ver_82AEP[] = { &maxRev, NULL, NULL };
1616

1717
static bool parse_entry(const uint8_t* data, uint32_t entry, uint32_t* addr) {
1818
if (entry + 4 >= SIZE_BOOTCODE) {

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