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1. Tiny_SoC Tiny_SoC Public

   This is my hobby project, which contain my rsic-v core and my convolutional layer with AMBA bus

   Verilog 2

2. Tiny_LeViT_Hardware_Accelerator Tiny_LeViT_Hardware_Accelerator Public

   This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.

   SystemVerilog 9

3. OpenSoCFabric OpenSoCFabric Public

   Forked from schoeberl/OpenSoCFabric

   OpenSoC Fabric - A Network-On-Chip Generator

   Scala 4

4. RISC-V-five-stage-CPU RISC-V-five-stage-CPU Public

   This is a project base on book 'Digital design and computer architure RISC-V edition'. I use Verilog to build RISC-V CPU.

   Verilog 2

5. Network-on-Chip-Router-Based-on-Packet-Connected-Circuit Network-on-Chip-Router-Based-on-Packet-Connected-Circuit Public archive

   This is my bachelor graduation project. It's a Network on Chip using by Verilog HDL. This 2D-Mesh NoC based on packet connected circuit.

   Verilog 5

6. BoChen-Ye.github.io BoChen-Ye.github.io Public

   Forked from RayeRen/acad-homepage.github.io

   AcadHomepage: A Modern and Responsive Academic Personal Homepage

   SCSS 1