[STM32Fxxx] Fix issue ARMmbed#816

Both STM32F0xx and STM32F1xx are using a 16-bit timer as a internal ticker
but the mBed ticker needs a 32-bit timer implementation, so the upper part
of that 32-bit timer is being calculated in software.

Software bug has been fixed where continous HIGH/LOW voltage levels
could be observerd for 65ms due to 16-bit timer overflow.

Now current value of TIM_MST->CNT is stored in cnt_val and is
updated in interrupt context only. This avoids master timer
overflow without SlaveCounter update.

This fix is only for platforms which already implements a 16-bit timer:
F103RB, F070RB, F030R8

Change-Id: I205c70ce155b373c6593ead93ade9ec38993f7f9

Author: kulaaraf

hal/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c

@@ -41,6 +41,7 @@ static int us_ticker_inited = 0;
 volatile uint32_t SlaveCounter = 0;
 volatile uint32_t oc_int_part = 0;
 volatile uint16_t oc_rem_part = 0;
+volatile uint16_t cnt_val = 0;
 
 void set_compare(uint16_t count) {
     TimMasterHandle.Instance = TIM_MST;
@@ -58,24 +59,15 @@ void us_ticker_init(void) {
 }
 
 uint32_t us_ticker_read() {
-    uint32_t counter, counter2;
+    uint32_t counter;
     if (!us_ticker_inited) us_ticker_init();
-    // A situation might appear when Master overflows right after Slave is read and before the
-    // new (overflowed) value of Master is read. Which would make the code below consider the
-    // previous (incorrect) value of Slave and the new value of Master, which would return a
-    // value in the past. Avoid this by computing consecutive values of the timer until they
-    // are properly ordered.
+
+    //Current value of TIM_MST->CNT is stored in cnt_val and is
+    //updated in interrupt context
     counter = (uint32_t)(SlaveCounter << 16);
-    counter += TIM_MST->CNT;
-    while (1) {
-        counter2 = (uint32_t)(SlaveCounter << 16);
-        counter2 += TIM_MST->CNT;
-        if (counter2 > counter) {
-            break;
-        }
-        counter = counter2;
-    }
-    return counter2;
+    counter += cnt_val;
+
+    return counter;
 }
 
 void us_ticker_set_interrupt(timestamp_t timestamp) {

hal/targets/hal/TARGET_STM/TARGET_STM32F1/us_ticker.c

@@ -38,6 +38,7 @@ static int us_ticker_inited = 0;
 volatile uint32_t SlaveCounter = 0;
 volatile uint32_t oc_int_part = 0;
 volatile uint16_t oc_rem_part = 0;
+volatile uint16_t cnt_val = 0;
 
 void set_compare(uint16_t count)
 {
@@ -58,24 +59,15 @@ void us_ticker_init(void)
 
 uint32_t us_ticker_read()
 {
-    uint32_t counter, counter2;
+    uint32_t counter;
     if (!us_ticker_inited) us_ticker_init();
-    // A situation might appear when Master overflows right after Slave is read and before the
-    // new (overflowed) value of Master is read. Which would make the code below consider the
-    // previous (incorrect) value of Slave and the new value of Master, which would return a
-    // value in the past. Avoid this by computing consecutive values of the timer until they
-    // are properly ordered.
+
+    //Current value of TIM_MST->CNT is stored in cnt_val and is
+    //updated in interrupt context
     counter = (uint32_t)(SlaveCounter << 16);
-    counter += TIM_MST->CNT;
-    while (1) {
-        counter2 = (uint32_t)(SlaveCounter << 16);
-        counter2 += TIM_MST->CNT;
-        if (counter2 > counter) {
-            break;
-        }
-        counter = counter2;
-    }
-    return counter2;
+    counter += cnt_val;
+
+    return counter;
 }
 
 void us_ticker_set_interrupt(timestamp_t timestamp)