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cassini.c
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/* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
*
* Copyright (C) 2004 Sun Microsystems Inc.
* Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
* 02111-1307, USA.
*
* This driver uses the sungem driver (c) David Miller
* (davem@redhat.com) as its basis.
*
* The cassini chip has a number of features that distinguish it from
* the gem chip:
* 4 transmit descriptor rings that are used for either QoS (VLAN) or
* load balancing (non-VLAN mode)
* batching of multiple packets
* multiple CPU dispatching
* page-based RX descriptor engine with separate completion rings
* Gigabit support (GMII and PCS interface)
* MIF link up/down detection works
*
* RX is handled by page sized buffers that are attached as fragments to
* the skb. here's what's done:
* -- driver allocates pages at a time and keeps reference counts
* on them.
* -- the upper protocol layers assume that the header is in the skb
* itself. as a result, cassini will copy a small amount (64 bytes)
* to make them happy.
* -- driver appends the rest of the data pages as frags to skbuffs
* and increments the reference count
* -- on page reclamation, the driver swaps the page with a spare page.
* if that page is still in use, it frees its reference to that page,
* and allocates a new page for use. otherwise, it just recycles the
* the page.
*
* NOTE: cassini can parse the header. however, it's not worth it
* as long as the network stack requires a header copy.
*
* TX has 4 queues. currently these queues are used in a round-robin
* fashion for load balancing. They can also be used for QoS. for that
* to work, however, QoS information needs to be exposed down to the driver
* level so that subqueues get targetted to particular transmit rings.
* alternatively, the queues can be configured via use of the all-purpose
* ioctl.
*
* RX DATA: the rx completion ring has all the info, but the rx desc
* ring has all of the data. RX can conceivably come in under multiple
* interrupts, but the INT# assignment needs to be set up properly by
* the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
* that. also, the two descriptor rings are designed to distinguish between
* encrypted and non-encrypted packets, but we use them for buffering
* instead.
*
* by default, the selective clear mask is set up to process rx packets.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/compiler.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/list.h>
#include <linux/dma-mapping.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/crc32.h>
#include <linux/random.h>
#include <linux/mii.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/mutex.h>
#include <net/checksum.h>
#include <asm/atomic.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <asm/uaccess.h>
#define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
#define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
#define CAS_NCPUS num_online_cpus()
#if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
#define USE_NAPI
#define cas_skb_release(x) netif_receive_skb(x)
#else
#define cas_skb_release(x) netif_rx(x)
#endif
/* select which firmware to use */
#define USE_HP_WORKAROUND
#define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
#define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
#include "cassini.h"
#define USE_TX_COMPWB /* use completion writeback registers */
#define USE_CSMA_CD_PROTO /* standard CSMA/CD */
#define USE_RX_BLANK /* hw interrupt mitigation */
#undef USE_ENTROPY_DEV /* don't test for entropy device */
/* NOTE: these aren't useable unless PCI interrupts can be assigned.
* also, we need to make cp->lock finer-grained.
*/
#undef USE_PCI_INTB
#undef USE_PCI_INTC
#undef USE_PCI_INTD
#undef USE_QOS
#undef USE_VPD_DEBUG /* debug vpd information if defined */
/* rx processing options */
#define USE_PAGE_ORDER /* specify to allocate large rx pages */
#define RX_DONT_BATCH 0 /* if 1, don't batch flows */
#define RX_COPY_ALWAYS 0 /* if 0, use frags */
#define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
#undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
#define DRV_MODULE_NAME "cassini"
#define PFX DRV_MODULE_NAME ": "
#define DRV_MODULE_VERSION "1.6"
#define DRV_MODULE_RELDATE "21 May 2008"
#define CAS_DEF_MSG_ENABLE \
(NETIF_MSG_DRV | \
NETIF_MSG_PROBE | \
NETIF_MSG_LINK | \
NETIF_MSG_TIMER | \
NETIF_MSG_IFDOWN | \
NETIF_MSG_IFUP | \
NETIF_MSG_RX_ERR | \
NETIF_MSG_TX_ERR)
/* length of time before we decide the hardware is borked,
* and dev->tx_timeout() should be called to fix the problem
*/
#define CAS_TX_TIMEOUT (HZ)
#define CAS_LINK_TIMEOUT (22*HZ/10)
#define CAS_LINK_FAST_TIMEOUT (1)
/* timeout values for state changing. these specify the number
* of 10us delays to be used before giving up.
*/
#define STOP_TRIES_PHY 1000
#define STOP_TRIES 5000
/* specify a minimum frame size to deal with some fifo issues
* max mtu == 2 * page size - ethernet header - 64 - swivel =
* 2 * page_size - 0x50
*/
#define CAS_MIN_FRAME 97
#define CAS_1000MB_MIN_FRAME 255
#define CAS_MIN_MTU 60
#define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
#if 1
/*
* Eliminate these and use separate atomic counters for each, to
* avoid a race condition.
*/
#else
#define CAS_RESET_MTU 1
#define CAS_RESET_ALL 2
#define CAS_RESET_SPARE 3
#endif
static char version[] __devinitdata =
DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
static int link_mode;
MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
MODULE_LICENSE("GPL");
module_param(cassini_debug, int, 0);
MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
module_param(link_mode, int, 0);
MODULE_PARM_DESC(link_mode, "default link mode");
/*
* Work around for a PCS bug in which the link goes down due to the chip
* being confused and never showing a link status of "up."
*/
#define DEFAULT_LINKDOWN_TIMEOUT 5
/*
* Value in seconds, for user input.
*/
static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
module_param(linkdown_timeout, int, 0);
MODULE_PARM_DESC(linkdown_timeout,
"min reset interval in sec. for PCS linkdown issue; disabled if not positive");
/*
* value in 'ticks' (units used by jiffies). Set when we init the
* module because 'HZ' in actually a function call on some flavors of
* Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
*/
static int link_transition_timeout;
static u16 link_modes[] __devinitdata = {
BMCR_ANENABLE, /* 0 : autoneg */
0, /* 1 : 10bt half duplex */
BMCR_SPEED100, /* 2 : 100bt half duplex */
BMCR_FULLDPLX, /* 3 : 10bt full duplex */
BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
};
static struct pci_device_id cas_pci_tbl[] __devinitdata = {
{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
static void cas_set_link_modes(struct cas *cp);
static inline void cas_lock_tx(struct cas *cp)
{
int i;
for (i = 0; i < N_TX_RINGS; i++)
spin_lock(&cp->tx_lock[i]);
}
static inline void cas_lock_all(struct cas *cp)
{
spin_lock_irq(&cp->lock);
cas_lock_tx(cp);
}
/* WTZ: QA was finding deadlock problems with the previous
* versions after long test runs with multiple cards per machine.
* See if replacing cas_lock_all with safer versions helps. The
* symptoms QA is reporting match those we'd expect if interrupts
* aren't being properly restored, and we fixed a previous deadlock
* with similar symptoms by using save/restore versions in other
* places.
*/
#define cas_lock_all_save(cp, flags) \
do { \
struct cas *xxxcp = (cp); \
spin_lock_irqsave(&xxxcp->lock, flags); \
cas_lock_tx(xxxcp); \
} while (0)
static inline void cas_unlock_tx(struct cas *cp)
{
int i;
for (i = N_TX_RINGS; i > 0; i--)
spin_unlock(&cp->tx_lock[i - 1]);
}
static inline void cas_unlock_all(struct cas *cp)
{
cas_unlock_tx(cp);
spin_unlock_irq(&cp->lock);
}
#define cas_unlock_all_restore(cp, flags) \
do { \
struct cas *xxxcp = (cp); \
cas_unlock_tx(xxxcp); \
spin_unlock_irqrestore(&xxxcp->lock, flags); \
} while (0)
static void cas_disable_irq(struct cas *cp, const int ring)
{
/* Make sure we won't get any more interrupts */
if (ring == 0) {
writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
return;
}
/* disable completion interrupts and selectively mask */
if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
switch (ring) {
#if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
#ifdef USE_PCI_INTB
case 1:
#endif
#ifdef USE_PCI_INTC
case 2:
#endif
#ifdef USE_PCI_INTD
case 3:
#endif
writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
cp->regs + REG_PLUS_INTRN_MASK(ring));
break;
#endif
default:
writel(INTRN_MASK_CLEAR_ALL, cp->regs +
REG_PLUS_INTRN_MASK(ring));
break;
}
}
}
static inline void cas_mask_intr(struct cas *cp)
{
int i;
for (i = 0; i < N_RX_COMP_RINGS; i++)
cas_disable_irq(cp, i);
}
static void cas_enable_irq(struct cas *cp, const int ring)
{
if (ring == 0) { /* all but TX_DONE */
writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
return;
}
if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
switch (ring) {
#if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
#ifdef USE_PCI_INTB
case 1:
#endif
#ifdef USE_PCI_INTC
case 2:
#endif
#ifdef USE_PCI_INTD
case 3:
#endif
writel(INTRN_MASK_RX_EN, cp->regs +
REG_PLUS_INTRN_MASK(ring));
break;
#endif
default:
break;
}
}
}
static inline void cas_unmask_intr(struct cas *cp)
{
int i;
for (i = 0; i < N_RX_COMP_RINGS; i++)
cas_enable_irq(cp, i);
}
static inline void cas_entropy_gather(struct cas *cp)
{
#ifdef USE_ENTROPY_DEV
if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
return;
batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
readl(cp->regs + REG_ENTROPY_IV),
sizeof(uint64_t)*8);
#endif
}
static inline void cas_entropy_reset(struct cas *cp)
{
#ifdef USE_ENTROPY_DEV
if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
return;
writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
cp->regs + REG_BIM_LOCAL_DEV_EN);
writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
/* if we read back 0x0, we don't have an entropy device */
if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
#endif
}
/* access to the phy. the following assumes that we've initialized the MIF to
* be in frame rather than bit-bang mode
*/
static u16 cas_phy_read(struct cas *cp, int reg)
{
u32 cmd;
int limit = STOP_TRIES_PHY;
cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
cmd |= MIF_FRAME_TURN_AROUND_MSB;
writel(cmd, cp->regs + REG_MIF_FRAME);
/* poll for completion */
while (limit-- > 0) {
udelay(10);
cmd = readl(cp->regs + REG_MIF_FRAME);
if (cmd & MIF_FRAME_TURN_AROUND_LSB)
return (cmd & MIF_FRAME_DATA_MASK);
}
return 0xFFFF; /* -1 */
}
static int cas_phy_write(struct cas *cp, int reg, u16 val)
{
int limit = STOP_TRIES_PHY;
u32 cmd;
cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
cmd |= MIF_FRAME_TURN_AROUND_MSB;
cmd |= val & MIF_FRAME_DATA_MASK;
writel(cmd, cp->regs + REG_MIF_FRAME);
/* poll for completion */
while (limit-- > 0) {
udelay(10);
cmd = readl(cp->regs + REG_MIF_FRAME);
if (cmd & MIF_FRAME_TURN_AROUND_LSB)
return 0;
}
return -1;
}
static void cas_phy_powerup(struct cas *cp)
{
u16 ctl = cas_phy_read(cp, MII_BMCR);
if ((ctl & BMCR_PDOWN) == 0)
return;
ctl &= ~BMCR_PDOWN;
cas_phy_write(cp, MII_BMCR, ctl);
}
static void cas_phy_powerdown(struct cas *cp)
{
u16 ctl = cas_phy_read(cp, MII_BMCR);
if (ctl & BMCR_PDOWN)
return;
ctl |= BMCR_PDOWN;
cas_phy_write(cp, MII_BMCR, ctl);
}
/* cp->lock held. note: the last put_page will free the buffer */
static int cas_page_free(struct cas *cp, cas_page_t *page)
{
pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
PCI_DMA_FROMDEVICE);
__free_pages(page->buffer, cp->page_order);
kfree(page);
return 0;
}
#ifdef RX_COUNT_BUFFERS
#define RX_USED_ADD(x, y) ((x)->used += (y))
#define RX_USED_SET(x, y) ((x)->used = (y))
#else
#define RX_USED_ADD(x, y)
#define RX_USED_SET(x, y)
#endif
/* local page allocation routines for the receive buffers. jumbo pages
* require at least 8K contiguous and 8K aligned buffers.
*/
static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
{
cas_page_t *page;
page = kmalloc(sizeof(cas_page_t), flags);
if (!page)
return NULL;
INIT_LIST_HEAD(&page->list);
RX_USED_SET(page, 0);
page->buffer = alloc_pages(flags, cp->page_order);
if (!page->buffer)
goto page_err;
page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
cp->page_size, PCI_DMA_FROMDEVICE);
return page;
page_err:
kfree(page);
return NULL;
}
/* initialize spare pool of rx buffers, but allocate during the open */
static void cas_spare_init(struct cas *cp)
{
spin_lock(&cp->rx_inuse_lock);
INIT_LIST_HEAD(&cp->rx_inuse_list);
spin_unlock(&cp->rx_inuse_lock);
spin_lock(&cp->rx_spare_lock);
INIT_LIST_HEAD(&cp->rx_spare_list);
cp->rx_spares_needed = RX_SPARE_COUNT;
spin_unlock(&cp->rx_spare_lock);
}
/* used on close. free all the spare buffers. */
static void cas_spare_free(struct cas *cp)
{
struct list_head list, *elem, *tmp;
/* free spare buffers */
INIT_LIST_HEAD(&list);
spin_lock(&cp->rx_spare_lock);
list_splice_init(&cp->rx_spare_list, &list);
spin_unlock(&cp->rx_spare_lock);
list_for_each_safe(elem, tmp, &list) {
cas_page_free(cp, list_entry(elem, cas_page_t, list));
}
INIT_LIST_HEAD(&list);
#if 1
/*
* Looks like Adrian had protected this with a different
* lock than used everywhere else to manipulate this list.
*/
spin_lock(&cp->rx_inuse_lock);
list_splice_init(&cp->rx_inuse_list, &list);
spin_unlock(&cp->rx_inuse_lock);
#else
spin_lock(&cp->rx_spare_lock);
list_splice_init(&cp->rx_inuse_list, &list);
spin_unlock(&cp->rx_spare_lock);
#endif
list_for_each_safe(elem, tmp, &list) {
cas_page_free(cp, list_entry(elem, cas_page_t, list));
}
}
/* replenish spares if needed */
static void cas_spare_recover(struct cas *cp, const gfp_t flags)
{
struct list_head list, *elem, *tmp;
int needed, i;
/* check inuse list. if we don't need any more free buffers,
* just free it
*/
/* make a local copy of the list */
INIT_LIST_HEAD(&list);
spin_lock(&cp->rx_inuse_lock);
list_splice_init(&cp->rx_inuse_list, &list);
spin_unlock(&cp->rx_inuse_lock);
list_for_each_safe(elem, tmp, &list) {
cas_page_t *page = list_entry(elem, cas_page_t, list);
if (page_count(page->buffer) > 1)
continue;
list_del(elem);
spin_lock(&cp->rx_spare_lock);
if (cp->rx_spares_needed > 0) {
list_add(elem, &cp->rx_spare_list);
cp->rx_spares_needed--;
spin_unlock(&cp->rx_spare_lock);
} else {
spin_unlock(&cp->rx_spare_lock);
cas_page_free(cp, page);
}
}
/* put any inuse buffers back on the list */
if (!list_empty(&list)) {
spin_lock(&cp->rx_inuse_lock);
list_splice(&list, &cp->rx_inuse_list);
spin_unlock(&cp->rx_inuse_lock);
}
spin_lock(&cp->rx_spare_lock);
needed = cp->rx_spares_needed;
spin_unlock(&cp->rx_spare_lock);
if (!needed)
return;
/* we still need spares, so try to allocate some */
INIT_LIST_HEAD(&list);
i = 0;
while (i < needed) {
cas_page_t *spare = cas_page_alloc(cp, flags);
if (!spare)
break;
list_add(&spare->list, &list);
i++;
}
spin_lock(&cp->rx_spare_lock);
list_splice(&list, &cp->rx_spare_list);
cp->rx_spares_needed -= i;
spin_unlock(&cp->rx_spare_lock);
}
/* pull a page from the list. */
static cas_page_t *cas_page_dequeue(struct cas *cp)
{
struct list_head *entry;
int recover;
spin_lock(&cp->rx_spare_lock);
if (list_empty(&cp->rx_spare_list)) {
/* try to do a quick recovery */
spin_unlock(&cp->rx_spare_lock);
cas_spare_recover(cp, GFP_ATOMIC);
spin_lock(&cp->rx_spare_lock);
if (list_empty(&cp->rx_spare_list)) {
if (netif_msg_rx_err(cp))
printk(KERN_ERR "%s: no spare buffers "
"available.\n", cp->dev->name);
spin_unlock(&cp->rx_spare_lock);
return NULL;
}
}
entry = cp->rx_spare_list.next;
list_del(entry);
recover = ++cp->rx_spares_needed;
spin_unlock(&cp->rx_spare_lock);
/* trigger the timer to do the recovery */
if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
#if 1
atomic_inc(&cp->reset_task_pending);
atomic_inc(&cp->reset_task_pending_spare);
schedule_work(&cp->reset_task);
#else
atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
schedule_work(&cp->reset_task);
#endif
}
return list_entry(entry, cas_page_t, list);
}
static void cas_mif_poll(struct cas *cp, const int enable)
{
u32 cfg;
cfg = readl(cp->regs + REG_MIF_CFG);
cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
if (cp->phy_type & CAS_PHY_MII_MDIO1)
cfg |= MIF_CFG_PHY_SELECT;
/* poll and interrupt on link status change. */
if (enable) {
cfg |= MIF_CFG_POLL_EN;
cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
}
writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
cp->regs + REG_MIF_MASK);
writel(cfg, cp->regs + REG_MIF_CFG);
}
/* Must be invoked under cp->lock */
static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
{
u16 ctl;
#if 1
int lcntl;
int changed = 0;
int oldstate = cp->lstate;
int link_was_not_down = !(oldstate == link_down);
#endif
/* Setup link parameters */
if (!ep)
goto start_aneg;
lcntl = cp->link_cntl;
if (ep->autoneg == AUTONEG_ENABLE)
cp->link_cntl = BMCR_ANENABLE;
else {
cp->link_cntl = 0;
if (ep->speed == SPEED_100)
cp->link_cntl |= BMCR_SPEED100;
else if (ep->speed == SPEED_1000)
cp->link_cntl |= CAS_BMCR_SPEED1000;
if (ep->duplex == DUPLEX_FULL)
cp->link_cntl |= BMCR_FULLDPLX;
}
#if 1
changed = (lcntl != cp->link_cntl);
#endif
start_aneg:
if (cp->lstate == link_up) {
printk(KERN_INFO "%s: PCS link down.\n",
cp->dev->name);
} else {
if (changed) {
printk(KERN_INFO "%s: link configuration changed\n",
cp->dev->name);
}
}
cp->lstate = link_down;
cp->link_transition = LINK_TRANSITION_LINK_DOWN;
if (!cp->hw_running)
return;
#if 1
/*
* WTZ: If the old state was link_up, we turn off the carrier
* to replicate everything we do elsewhere on a link-down
* event when we were already in a link-up state..
*/
if (oldstate == link_up)
netif_carrier_off(cp->dev);
if (changed && link_was_not_down) {
/*
* WTZ: This branch will simply schedule a full reset after
* we explicitly changed link modes in an ioctl. See if this
* fixes the link-problems we were having for forced mode.
*/
atomic_inc(&cp->reset_task_pending);
atomic_inc(&cp->reset_task_pending_all);
schedule_work(&cp->reset_task);
cp->timer_ticks = 0;
mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
return;
}
#endif
if (cp->phy_type & CAS_PHY_SERDES) {
u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
if (cp->link_cntl & BMCR_ANENABLE) {
val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
cp->lstate = link_aneg;
} else {
if (cp->link_cntl & BMCR_FULLDPLX)
val |= PCS_MII_CTRL_DUPLEX;
val &= ~PCS_MII_AUTONEG_EN;
cp->lstate = link_force_ok;
}
cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
writel(val, cp->regs + REG_PCS_MII_CTRL);
} else {
cas_mif_poll(cp, 0);
ctl = cas_phy_read(cp, MII_BMCR);
ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
ctl |= cp->link_cntl;
if (ctl & BMCR_ANENABLE) {
ctl |= BMCR_ANRESTART;
cp->lstate = link_aneg;
} else {
cp->lstate = link_force_ok;
}
cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
cas_phy_write(cp, MII_BMCR, ctl);
cas_mif_poll(cp, 1);
}
cp->timer_ticks = 0;
mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
}
/* Must be invoked under cp->lock. */
static int cas_reset_mii_phy(struct cas *cp)
{
int limit = STOP_TRIES_PHY;
u16 val;
cas_phy_write(cp, MII_BMCR, BMCR_RESET);
udelay(100);
while (limit--) {
val = cas_phy_read(cp, MII_BMCR);
if ((val & BMCR_RESET) == 0)
break;
udelay(10);
}
return (limit <= 0);
}
static void cas_saturn_firmware_load(struct cas *cp)
{
cas_saturn_patch_t *patch = cas_saturn_patch;
cas_phy_powerdown(cp);
/* expanded memory access mode */
cas_phy_write(cp, DP83065_MII_MEM, 0x0);
/* pointer configuration for new firmware */
cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
cas_phy_write(cp, DP83065_MII_REGD, 0x82);
cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
cas_phy_write(cp, DP83065_MII_REGD, 0x0);
cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
cas_phy_write(cp, DP83065_MII_REGD, 0x39);
/* download new firmware */
cas_phy_write(cp, DP83065_MII_MEM, 0x1);
cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
while (patch->addr) {
cas_phy_write(cp, DP83065_MII_REGD, patch->val);
patch++;
}
/* enable firmware */
cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
cas_phy_write(cp, DP83065_MII_REGD, 0x1);
}
/* phy initialization */
static void cas_phy_init(struct cas *cp)
{
u16 val;
/* if we're in MII/GMII mode, set up phy */
if (CAS_PHY_MII(cp->phy_type)) {
writel(PCS_DATAPATH_MODE_MII,
cp->regs + REG_PCS_DATAPATH_MODE);
cas_mif_poll(cp, 0);
cas_reset_mii_phy(cp); /* take out of isolate mode */
if (PHY_LUCENT_B0 == cp->phy_id) {
/* workaround link up/down issue with lucent */
cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
cas_phy_write(cp, MII_BMCR, 0x00f1);
cas_phy_write(cp, LUCENT_MII_REG, 0x0);
} else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
/* workarounds for broadcom phy */
cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
} else if (PHY_BROADCOM_5411 == cp->phy_id) {
val = cas_phy_read(cp, BROADCOM_MII_REG4);
val = cas_phy_read(cp, BROADCOM_MII_REG4);
if (val & 0x0080) {
/* link workaround */
cas_phy_write(cp, BROADCOM_MII_REG4,
val & ~0x0080);
}
} else if (cp->cas_flags & CAS_FLAG_SATURN) {
writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
SATURN_PCFG_FSI : 0x0,
cp->regs + REG_SATURN_PCFG);
/* load firmware to address 10Mbps auto-negotiation
* issue. NOTE: this will need to be changed if the
* default firmware gets fixed.
*/
if (PHY_NS_DP83065 == cp->phy_id) {
cas_saturn_firmware_load(cp);
}
cas_phy_powerup(cp);
}
/* advertise capabilities */
val = cas_phy_read(cp, MII_BMCR);
val &= ~BMCR_ANENABLE;
cas_phy_write(cp, MII_BMCR, val);
udelay(10);
cas_phy_write(cp, MII_ADVERTISE,
cas_phy_read(cp, MII_ADVERTISE) |
(ADVERTISE_10HALF | ADVERTISE_10FULL |
ADVERTISE_100HALF | ADVERTISE_100FULL |
CAS_ADVERTISE_PAUSE |
CAS_ADVERTISE_ASYM_PAUSE));
if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
/* make sure that we don't advertise half
* duplex to avoid a chip issue
*/
val = cas_phy_read(cp, CAS_MII_1000_CTRL);
val &= ~CAS_ADVERTISE_1000HALF;
val |= CAS_ADVERTISE_1000FULL;
cas_phy_write(cp, CAS_MII_1000_CTRL, val);
}
} else {
/* reset pcs for serdes */
u32 val;
int limit;
writel(PCS_DATAPATH_MODE_SERDES,
cp->regs + REG_PCS_DATAPATH_MODE);
/* enable serdes pins on saturn */
if (cp->cas_flags & CAS_FLAG_SATURN)
writel(0, cp->regs + REG_SATURN_PCFG);
/* Reset PCS unit. */
val = readl(cp->regs + REG_PCS_MII_CTRL);
val |= PCS_MII_RESET;
writel(val, cp->regs + REG_PCS_MII_CTRL);
limit = STOP_TRIES;
while (limit-- > 0) {
udelay(10);
if ((readl(cp->regs + REG_PCS_MII_CTRL) &
PCS_MII_RESET) == 0)
break;
}
if (limit <= 0)
printk(KERN_WARNING "%s: PCS reset bit would not "
"clear [%08x].\n", cp->dev->name,
readl(cp->regs + REG_PCS_STATE_MACHINE));
/* Make sure PCS is disabled while changing advertisement
* configuration.
*/
writel(0x0, cp->regs + REG_PCS_CFG);
/* Advertise all capabilities except half-duplex. */
val = readl(cp->regs + REG_PCS_MII_ADVERT);
val &= ~PCS_MII_ADVERT_HD;
val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
PCS_MII_ADVERT_ASYM_PAUSE);
writel(val, cp->regs + REG_PCS_MII_ADVERT);
/* enable PCS */
writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
/* pcs workaround: enable sync detect */
writel(PCS_SERDES_CTRL_SYNCD_EN,
cp->regs + REG_PCS_SERDES_CTRL);
}
}
static int cas_pcs_link_check(struct cas *cp)
{
u32 stat, state_machine;
int retval = 0;
/* The link status bit latches on zero, so you must
* read it twice in such a case to see a transition
* to the link being up.
*/
stat = readl(cp->regs + REG_PCS_MII_STATUS);
if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
stat = readl(cp->regs + REG_PCS_MII_STATUS);
/* The remote-fault indication is only valid
* when autoneg has completed.
*/
if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
PCS_MII_STATUS_REMOTE_FAULT)) ==
(PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
if (netif_msg_link(cp))
printk(KERN_INFO "%s: PCS RemoteFault\n",
cp->dev->name);
}
/* work around link detection issue by querying the PCS state
* machine directly.
*/
state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
stat &= ~PCS_MII_STATUS_LINK_STATUS;
} else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
stat |= PCS_MII_STATUS_LINK_STATUS;
}