|
41 | 41 | /** |
42 | 42 | * Define Tx Power |
43 | 43 | */ |
44 | | -#define CFG_TX_POWER (0x18) /* -0.15dBm */ |
| 44 | +#ifndef CFG_TX_POWER |
| 45 | + #define CFG_TX_POWER (0x18) /* -0.15dBm */ |
| 46 | +#endif |
45 | 47 |
|
46 | 48 | /****************************************************************************** |
47 | 49 | * BLE Stack |
|
50 | 52 | * Maximum number of simultaneous connections that the device will support. |
51 | 53 | * Valid values are from 1 to 8 |
52 | 54 | */ |
53 | | -#define CFG_BLE_NUM_LINK 8 |
| 55 | +#ifndef CFG_BLE_NUM_LINK |
| 56 | + #define CFG_BLE_NUM_LINK 8 |
| 57 | +#endif |
54 | 58 |
|
55 | 59 | /** |
56 | 60 | * Maximum number of Services that can be stored in the GATT database. |
57 | 61 | * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services |
58 | 62 | */ |
59 | | -#define CFG_BLE_NUM_GATT_SERVICES 8 |
| 63 | +#ifndef CFG_BLE_NUM_GATT_SERVICES |
| 64 | + #define CFG_BLE_NUM_GATT_SERVICES 8 |
| 65 | +#endif |
60 | 66 |
|
61 | 67 | /** |
62 | 68 | * Maximum number of Attributes |
|
65 | 71 | * Note that certain characteristics and relative descriptors are added automatically during device initialization |
66 | 72 | * so this parameters should be 9 plus the number of user Attributes |
67 | 73 | */ |
68 | | -#define CFG_BLE_NUM_GATT_ATTRIBUTES 68 |
| 74 | +#ifndef CFG_BLE_NUM_GATT_ATTRIBUTES |
| 75 | + #define CFG_BLE_NUM_GATT_ATTRIBUTES 68 |
| 76 | +#endif |
69 | 77 |
|
70 | 78 | /** |
71 | 79 | * Maximum supported ATT_MTU size |
72 | 80 | * This parameter is ignored by the CPU2 when CFG_BLE_OPTIONS has SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY flag set |
73 | 81 | */ |
74 | | -#define CFG_BLE_MAX_ATT_MTU (156) |
| 82 | +#ifndef CFG_BLE_MAX_ATT_MTU |
| 83 | + #define CFG_BLE_MAX_ATT_MTU (156) |
| 84 | +#endif |
75 | 85 |
|
76 | 86 | /** |
77 | 87 | * Size of the storage area for Attribute values |
|
84 | 94 | * The total amount of memory needed is the sum of the above quantities for each attribute. |
85 | 95 | * This parameter is ignored by the CPU2 when CFG_BLE_OPTIONS has SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY flag set |
86 | 96 | */ |
87 | | -#define CFG_BLE_ATT_VALUE_ARRAY_SIZE (1344) |
| 97 | +#ifndef CFG_BLE_ATT_VALUE_ARRAY_SIZE |
| 98 | + #define CFG_BLE_ATT_VALUE_ARRAY_SIZE (1344) |
| 99 | +#endif |
88 | 100 |
|
89 | 101 | /** |
90 | 102 | * Prepare Write List size in terms of number of packet |
91 | 103 | * This parameter is ignored by the CPU2 when CFG_BLE_OPTIONS has SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY flag set |
92 | 104 | */ |
93 | 105 | // #define CFG_BLE_PREPARE_WRITE_LIST_SIZE BLE_PREP_WRITE_X_ATT(CFG_BLE_MAX_ATT_MTU) |
94 | | -#define CFG_BLE_PREPARE_WRITE_LIST_SIZE (0x3A) |
| 106 | +#ifndef CFG_BLE_PREPARE_WRITE_LIST_SIZE |
| 107 | + #define CFG_BLE_PREPARE_WRITE_LIST_SIZE (0x3A) |
| 108 | +#endif |
95 | 109 |
|
96 | 110 | /** |
97 | 111 | * Number of allocated memory blocks |
|
103 | 117 | /** |
104 | 118 | * Enable or disable the Extended Packet length feature. Valid values are 0 or 1. |
105 | 119 | */ |
106 | | -#define CFG_BLE_DATA_LENGTH_EXTENSION 1 |
| 120 | +#ifndef CFG_BLE_DATA_LENGTH_EXTENSION |
| 121 | + #define CFG_BLE_DATA_LENGTH_EXTENSION 1 |
| 122 | +#endif |
107 | 123 |
|
108 | 124 | /** |
109 | 125 | * Sleep clock accuracy in Slave mode (ppm value) |
110 | 126 | */ |
111 | | -#define CFG_BLE_SLAVE_SCA 500 |
| 127 | +#ifndef CFG_BLE_SLAVE_SCA |
| 128 | + #define CFG_BLE_SLAVE_SCA 500 |
| 129 | +#endif |
112 | 130 |
|
113 | 131 | /** |
114 | 132 | * Sleep clock accuracy in Master mode |
|
121 | 139 | * 6 : 21 ppm to 30 ppm |
122 | 140 | * 7 : 0 ppm to 20 ppm |
123 | 141 | */ |
124 | | -#define CFG_BLE_MASTER_SCA 0 |
| 142 | +#ifndef CFG_BLE_MASTER_SCA |
| 143 | + #define CFG_BLE_MASTER_SCA 0 |
| 144 | +#endif |
125 | 145 |
|
126 | 146 | /** |
127 | 147 | * LsSource |
|
130 | 150 | * - bit 1: 1: STM32WB5M Module device 0: Other devices as STM32WBxx SOC, STM32WB1M module |
131 | 151 | * - bit 2: 1: HSE/1024 Clock config 0: LSE Clock config |
132 | 152 | */ |
133 | | -#if defined(STM32WB5Mxx) |
134 | | - #define CFG_BLE_LS_SOURCE (SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LS_MOD5MM_DEV | SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE) |
135 | | -#else |
136 | | - #define CFG_BLE_LS_SOURCE (SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LS_OTHER_DEV | SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE) |
| 153 | +#ifndef CFG_BLE_LS_SOURCE |
| 154 | + #if defined(STM32WB5Mxx) |
| 155 | + #define CFG_BLE_LS_SOURCE (SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LS_MOD5MM_DEV | SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE) |
| 156 | + #else |
| 157 | + #define CFG_BLE_LS_SOURCE (SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LS_OTHER_DEV | SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE) |
| 158 | + #endif |
137 | 159 | #endif |
138 | 160 |
|
139 | 161 | /** |
140 | 162 | * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us) |
141 | 163 | */ |
142 | | -#define CFG_BLE_HSE_STARTUP_TIME 0x148 |
| 164 | +#ifndef CFG_BLE_HSE_STARTUP_TIME |
| 165 | + #define CFG_BLE_HSE_STARTUP_TIME 0x148 |
| 166 | +#endif |
143 | 167 |
|
144 | 168 | /** |
145 | 169 | * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us) |
146 | 170 | */ |
147 | | -#define CFG_BLE_MAX_CONN_EVENT_LENGTH (0xFFFFFFFF) |
| 171 | +#ifndef CFG_BLE_MAX_CONN_EVENT_LENGTH |
| 172 | + #define CFG_BLE_MAX_CONN_EVENT_LENGTH (0xFFFFFFFF) |
| 173 | +#endif |
148 | 174 |
|
149 | 175 | /** |
150 | 176 | * Viterbi Mode |
|
0 commit comments