first commit

Author: Alex Yazdani

4_to_16_decoder.v

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+/*
+Alex Yazdani
+18 November 2024
+4-to-16 Decoder
+
+Inputs:
+    in (4 bits): Input binary value
+    enable (1 bit): Enable signal
+
+Outputs:
+    out (16 bits): One-hot output based on the input value
+*/
+
+module decoder_4to16(
+    input [3:0] in,
+    input enable,
+    output reg [15:0] out
+);
+
+    always @(*) begin
+        if (enable) begin
+            out = 16'b0; // Default all outputs to 0
+            case (in)
+                4'b0000: out[0]  = 1;
+                4'b0001: out[1]  = 1;
+                4'b0010: out[2]  = 1;
+                4'b0011: out[3]  = 1;
+                4'b0100: out[4]  = 1;
+                4'b0101: out[5]  = 1;
+                4'b0110: out[6]  = 1;
+                4'b0111: out[7]  = 1;
+                4'b1000: out[8]  = 1;
+                4'b1001: out[9]  = 1;
+                4'b1010: out[10] = 1;
+                4'b1011: out[11] = 1;
+                4'b1100: out[12] = 1;
+                4'b1101: out[13] = 1;
+                4'b1110: out[14] = 1;
+                4'b1111: out[15] = 1;
+                default: out = 16'b0;
+            endcase
+        end else begin
+            out = 16'b0; // Outputs are all zero when enable is low
+        end
+    end
+
+endmodule

elevator.v

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+/*
+Alex Yazdani
+18 November 2024
+Elevator Controller Module
+
+Inputs:
+    clk
+    reset
+    req_floor (3 bits: floor request)
+
+Outputs:
+    current_floor (3 bits: current floor)
+    moving (1 bit: elevator moving indicator)
+
+States:
+    IDLE
+    MOVING_UP
+    MOVING_DOWN
+    ARRIVED
+*/
+
+module elevator_controller(
+    input clk, reset,
+    input [2:0] req_floor,
+    output reg [2:0] current_floor,
+    output reg moving
+);
+
+    // State Encoding
+    parameter IDLE = 2'b00;
+    parameter MOVING_UP = 2'b01;
+    parameter MOVING_DOWN = 2'b10;
+    parameter ARRIVED = 2'b11;
+
+    reg [1:0] state, next_state;
+
+    // State Memory
+    always @(posedge clk or posedge reset) begin
+        if (reset)
+            state <= IDLE;
+        else
+            state <= next_state;
+    end
+
+    // Next State Logic (NSL)
+    always @(*) begin
+        next_state = state; // Default to prevent latches
+        case (state)
+            IDLE: begin
+                if (req_floor > current_floor)
+                    next_state = MOVING_UP;
+                else if (req_floor < current_floor)
+                    next_state = MOVING_DOWN;
+            end
+            MOVING_UP: begin
+                if (current_floor == req_floor)
+                    next_state = ARRIVED;
+            end
+            MOVING_DOWN: begin
+                if (current_floor == req_floor)
+                    next_state = ARRIVED;
+            end
+            ARRIVED: next_state = IDLE;
+            default: next_state = IDLE;
+        endcase
+    end
+
+    // Output and Floor Logic
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            current_floor <= 3'd0; // Reset to ground floor
+            moving <= 1'b0;
+        end else begin
+            case (state)
+                MOVING_UP: begin
+                    current_floor <= current_floor + 1;
+                    moving <= 1'b1;
+                end
+                MOVING_DOWN: begin
+                    current_floor <= current_floor - 1;
+                    moving <= 1'b1;
+                end
+                ARRIVED: moving <= 1'b0;
+                default: moving <= 1'b0;
+            endcase
+        end
+    end
+
+endmodule

priority_encoder.v

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+/*
+Alex Yazdani
+18 November 2024
+4-to-2 Priority Encoder
+
+Inputs:
+    in (4 bits): Input signal
+Outputs:
+    out (2 bits): Encoded output
+    valid (1 bit): Indicates if any input is valid
+*/
+
+module priority_encoder(
+    input [3:0] in,
+    output reg [1:0] out,
+    output reg valid
+);
+
+    always @(*) begin
+        valid = 1'b0; // Default to no valid input
+        out = 2'b00;  // Default output value
+        casez (in)
+            4'b1???: begin
+                valid = 1'b1;
+                out = 2'b11;
+            end
+            4'b01??: begin
+                valid = 1'b1;
+                out = 2'b10;
+            end
+            4'b001?: begin
+                valid = 1'b1;
+                out = 2'b01;
+            end
+            4'b0001: begin
+                valid = 1'b1;
+                out = 2'b00;
+            end
+            default: begin
+                valid = 1'b0;
+                out = 2'b00;
+            end
+        endcase
+    end
+
+endmodule

rca.v

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+/*
+Alex Yazdani
+18 November 2024
+4-bit Ripple Carry Adder
+
+Inputs:
+    A (4 bits): First operand
+    B (4 bits): Second operand
+    Cin (1 bit): Carry-in
+
+Outputs:
+    Sum (4 bits): Result of A + B + Cin
+    Cout (1 bit): Carry-out of the most significant bit
+*/
+
+module ripple_carry_adder(
+    input [3:0] A,
+    input [3:0] B,
+    input Cin,
+    output [3:0] Sum,
+    output Cout
+);
+
+    wire c1, c2, c3; // Internal carry signals
+
+    // Full Adder for bit 0
+    full_adder FA0 (
+        .a(A[0]),
+        .b(B[0]),
+        .cin(Cin),
+        .sum(Sum[0]),
+        .cout(c1)
+    );
+
+    // Full Adder for bit 1
+    full_adder FA1 (
+        .a(A[1]),
+        .b(B[1]),
+        .cin(c1),
+        .sum(Sum[1]),
+        .cout(c2)
+    );
+
+    // Full Adder for bit 2
+    full_adder FA2 (
+        .a(A[2]),
+        .b(B[2]),
+        .cin(c2),
+        .sum(Sum[2]),
+        .cout(c3)
+    );
+
+    // Full Adder for bit 3
+    full_adder FA3 (
+        .a(A[3]),
+        .b(B[3]),
+        .cin(c3),
+        .sum(Sum[3]),
+        .cout(Cout)
+    );
+
+endmodule
+
+// Full Adder Module
+module full_adder(
+    input a,
+    input b,
+    input cin,
+    output sum,
+    output cout
+);
+
+    assign sum = a ^ b ^ cin; // XOR for sum
+    assign cout = (a & b) | (b & cin) | (a & cin); // Carry-out logic
+
+endmodule

traffic_controller.v

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+/*
+Alex Yazdani
+18 November 2024
+Traffic Controller Module
+*/
+
+module traffic_controller(
+    input clk, reset, ped_req,
+    output [1:0] veh_light,
+    output ped_light
+);
+
+    // State Encoding
+    parameter IDLE = 2'b00;
+    parameter GREEN = 2'b01;
+    parameter YELLOW = 2'b10;
+    parameter RED = 2'b11;
+
+    reg [1:0] state, next_state;
+    reg [3:0] counter;
+
+    // Counter Logic
+    always @(posedge clk or posedge reset) begin
+        if (reset) counter <= 0;
+        else if (counter == 4'd9 && state == GREEN) counter <= 0;
+        else if (counter == 4'd4 && state == YELLOW) counter <= 0;
+        else if ((counter == 4'd9 && !ped_req) || (counter > 4'd9)) counter <= 0;
+        else if (state != next_state) counter <= 0;
+        else counter <= counter + 1;
+    end
+
+    // State Memory
+    always @(posedge clk or posedge reset) begin
+        if (reset) state <= IDLE;
+        else state <= next_state;
+    end
+
+    // Next State Logic (NSL)
+    always @(*) begin
+        next_state = state;
+        case (state)
+            IDLE:       next_state = GREEN;
+            GREEN:      if (counter == 4'd9) next_state = YELLOW;
+            YELLOW:     if (counter == 4'd4) next_state = RED;
+            RED:        if (((counter == 4'd9) && !ped_req) || (counter > 4'd9)) next_state = GREEN;
+            default:    next_state = IDLE;
+        endcase
+    end
+
+    // Output Logic (OFL)
+    assign veh_light = state;
+    assign ped_light = (state == RED);
+
+endmodule

vending_machine.v

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+/*
+Alex Yazdani
+18 November 2024
+Vending Machine Module
+
+Inputs:
+    clk
+    reset
+    coin
+    dispense
+
+Outputs:
+    water_out
+    status
+
+States:
+    IDLE
+    COIN_INSERTED
+    DISPENSE_WATER
+    DISPENSE_COMPLETE
+*/
+
+module vending_machine(
+    input clk, reset,
+    input coin, dispense,
+    output water_out,
+    output [1:0] status
+);
+
+    // State Encoding
+    parameter IDLE = 2'b00;
+    parameter COIN_INSERTED = 2'b01;
+    parameter DISPENSE_WATER = 2'b10;
+    parameter DISPENSE_COMPLETE = 2'b11;
+
+    // Counter Logic
+    reg [2:0] counter;
+    always @(posedge clk) begin
+        if (reset) counter <= 3'd0;
+        else if (state == DISPENSE_WATER) begin
+            if (counter == 3'd4) counter <= 3'd0;
+            else counter <= counter + 1;
+        end else counter <= 3'd0;
+    end
+
+    // State Memory
+    reg [1:0] state, next_state;
+    always @(posedge clk) begin
+        if (reset) state <= IDLE;
+        else state <= next_state;
+    end
+
+    // Next State Logic
+    always @(*) begin
+        next_state = state;
+        case (state)
+            IDLE:               if (coin) next_state = COIN_INSERTED;
+            COIN_INSERTED:      if (dispense) next_state = DISPENSE_WATER;
+            DISPENSE_WATER:     if (counter == 3'd4) next_state = DISPENSE_COMPLETE;
+            DISPENSE_COMPLETE:  next_state = IDLE;
+            default:            next_state = IDLE;
+        endcase
+    end
+
+    // Output Function Logic
+    assign water_out = (state == DISPENSE_WATER);
+    assign status = state;
+
+endmodule