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Alex YazdaniAlex Yazdani
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added fifo.v
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fifo.v

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/*
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Alexander Yazdani
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2 December 2024
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Synchronous and Asynchronous FIFO Implementations
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*/
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module fifo_synch #(
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parameter DATA_WIDTH = 8,
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parameter DEPTH = 16
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)(
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input clk,
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input reset,
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input write_en,
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input read_en,
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input [DATA_WIDTH-1:0] d_in,
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output reg [DATA_WIDTH-1:0] d_out,
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output full,
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output empty
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);
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reg [DATA_WIDTH-1:0] memory [0:DEPTH-1];
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reg [$clog2(DEPTH)-1:0] write_ptr;
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reg [$clog2(DEPTH)-1:0] read_ptr;
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reg [$clog2(DEPTH):0] count;
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always @(posedge clk) begin
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if (reset) begin
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write_ptr <= 0;
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read_ptr <= 0;
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d_out <= 0;
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count <= 0;
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end else begin
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if (write_en && !full) begin
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memory[write_ptr] <= d_in;
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write_ptr <= (write_ptr + 1) % DEPTH;
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count <= count + 1;
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end
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if (read_en && !empty) begin
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d_out <= memory[read_ptr];
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read_ptr <= (read_ptr + 1) % DEPTH;
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count <= count - 1;
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end
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end
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end
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assign full = (count == DEPTH);
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assign empty = (count == 0);
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endmodule

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