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lines changed Original file line number Diff line number Diff line change 1+ /*
2+ Alexander Yazdani
3+ 2 December 2024
4+ Synchronous and Asynchronous FIFO Implementations
5+ */
6+
7+ module fifo_synch #(
8+ parameter DATA_WIDTH = 8 ,
9+ parameter DEPTH = 16
10+ )(
11+ input clk,
12+ input reset,
13+ input write_en,
14+ input read_en,
15+ input [DATA_WIDTH- 1 :0 ] d_in,
16+ output reg [DATA_WIDTH- 1 :0 ] d_out,
17+ output full,
18+ output empty
19+ );
20+
21+ reg [DATA_WIDTH- 1 :0 ] memory [0 :DEPTH- 1 ];
22+ reg [$clog2(DEPTH)- 1 :0 ] write_ptr;
23+ reg [$clog2(DEPTH)- 1 :0 ] read_ptr;
24+ reg [$clog2(DEPTH):0 ] count;
25+
26+
27+ always @(posedge clk) begin
28+ if (reset) begin
29+ write_ptr <= 0 ;
30+ read_ptr <= 0 ;
31+ d_out <= 0 ;
32+ count <= 0 ;
33+ end else begin
34+ if (write_en && ! full) begin
35+ memory[write_ptr] <= d_in;
36+ write_ptr <= (write_ptr + 1 ) % DEPTH;
37+ count <= count + 1 ;
38+ end
39+ if (read_en && ! empty) begin
40+ d_out <= memory[read_ptr];
41+ read_ptr <= (read_ptr + 1 ) % DEPTH;
42+ count <= count - 1 ;
43+ end
44+ end
45+ end
46+
47+ assign full = (count == DEPTH);
48+ assign empty = (count == 0 );
49+
50+ endmodule
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