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This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for EDA.

TeX 138 21 Updated Jun 19, 2024

Cross-platform GUI for Git. Built with Monaco Editor and Electron.

Vue 144 2 Updated Dec 28, 2024

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

SystemVerilog 57 6 Updated Nov 28, 2024

Huly — All-in-One Project Management Platform (alternative to Linear, Jira, Slack, Notion, Motion)

TypeScript 18,090 1,111 Updated Jan 7, 2025

SystemVerilog synthesis tool

Verilog 176 23 Updated Jan 7, 2025

smelt is a library to create, execute and analyze integration tests

Rust 25 Updated Dec 6, 2024
C 597 47 Updated Dec 18, 2024

Open Logic FPGA Standard Library

VHDL 401 34 Updated Jan 1, 2025
Jupyter Notebook 68 13 Updated Dec 9, 2024

APB master and slave developed in RTL.

SystemVerilog 10 1 Updated Aug 2, 2024

A new Hardware Design Language that keeps you in the driver's seat

Rust 70 5 Updated Dec 18, 2024

A General-Purpose Versioned-Dependency Manager

Go 194 2 Updated Aug 27, 2024

A modeling library with virtual components for SystemC and TLM simulators

C++ 137 35 Updated Dec 21, 2024

SigLib Digital Signal Processing and Machine Learning Library

C 98 21 Updated Dec 6, 2024

⏣ React for Circuits

TypeScript 579 19 Updated Jan 7, 2025

Linux capable RISC-V SoC designed to be readable and useful.

C 133 9 Updated Oct 17, 2024
Verilog 1,292 278 Updated Dec 26, 2024

PCI express simulation framework for Cocotb

Python 144 48 Updated Nov 28, 2023
C 14 1 Updated Sep 9, 2024

32-bit RISC-V Emulator

C 23 1 Updated Feb 23, 2019

A kernel designed to run one and only one application in a virtualized environment

C 2,683 139 Updated Dec 22, 2024

Unified Access Page for the TRISTAN project

HTML 12 30 Updated Nov 27, 2024

Simple UVM environment for experimenting with Verilator.

SystemVerilog 13 1 Updated Jan 1, 2025

The Perun2 Programming Language

C++ 76 Updated Dec 16, 2024
SystemVerilog 79 5 Updated Apr 16, 2024

RISC-V Embedded Processor for Approximate Computing

Verilog 121 80 Updated Nov 2, 2024

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

C 350 24 Updated Jan 7, 2025
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