Verilog Ethernet components for FPGA implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RTL, Cmodel, and testbench for NVDLA

Open source FPGA-based NIC and platform for in-network compute

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

HDL libraries and projects

A small, light weight, RISC CPU soft core

RISC-V CPU Core (RV32IM)

Verilog library for ASIC and FPGA designers

OpenXuantie - OpenC910 Core

Verilog PCI express components

An Open-source FPGA IP Generator

3-stage RV32IMACZb* processor with debug

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

RISC-V Formal Verification Framework

A High-performance Timing Analysis Tool for VLSI Systems

VRoom! RISC-V CPU

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

FuseSoC-based SoC for VeeR EH1 and EL2

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

A simple, basic, formally verified UART controller

The USRP™ Hardware Driver FPGA Repository

A Verilog implementation of DisplayPort protocol for FPGAs

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.

SystemVerilog synthesis tool

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core