Executable program which do some lint checks on Verilog code.
- Arithmetic Overflow
- Unreachable FSM State
- Un-initialized Register
- Multi-Driven Bus
- Non Full/Parallel Case
Detailed documentation on how each check is made can be found in document.docx
Illustrative video for the documetation (in Arabic). Video Link: https://drive.google.com/file/d/1APKrQv6z8x30UTBz93RUfHYs6-vAUoP4/view?usp=sharing