Skip to content

Commit 5daad96

Browse files
0xc01700xc0170
authored
Merge pull request #12950 from artokin/feature_wisun_nanostack_12_2_0
[feature-wisun] Nanostack release 12.2.0
2 parents 99c1667 + eeaa917 commit 5daad96

File tree

98 files changed

+5408
-1049
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

98 files changed

+5408
-1049
lines changed

‎components/802.15.4_RF/atmel-rf-driver/source/AT86RF215Reg.h‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,9 @@ extern "C" {
5555
#define BBC_TXFLH 0x07
5656
#define BBC_FBLL 0x08
5757
#define BBC_FBLH 0x09
58+
#define BBC_OFDMPHRTX 0x0C
59+
#define BBC_OFDMC 0x0E
60+
#define BBC_OFDMSW 0x0F
5861
#define BBC_OQPSKC0 0x10
5962
#define BBC_OQPSKC1 0x11
6063
#define BBC_OQPSKC2 0x12
@@ -90,6 +93,7 @@ extern "C" {
9093
// RF_AGCS
9194
#define TGT 0xE0
9295
#define TGT_1 (1 << 5)
96+
#define TGT_3 (3 << 5)
9397

9498

9599
// RF_RXBWC
@@ -131,6 +135,7 @@ extern "C" {
131135
// RF_TXDFE, RF_RXDFE
132136
#define RCUT 0xE0
133137
#define RCUT_4 (4 << 5)
138+
#define RCUT_3 (3 << 5)
134139
#define RCUT_2 (2 << 5)
135140
#define RCUT_1 (1 << 5)
136141
#define RCUT_0 (0 << 5)
@@ -144,6 +149,41 @@ extern "C" {
144149
#define SR_2 (2 << 0)
145150
#define SR_1 (1 << 0)
146151

152+
// BBC_OFDMPHRTX
153+
#define MCS 0x07
154+
#define MCS_0 (0 << 0)
155+
#define MCS_1 (1 << 0)
156+
#define MCS_2 (2 << 0)
157+
#define MCS_3 (3 << 0)
158+
#define MCS_4 (4 << 0)
159+
#define MCS_5 (5 << 0)
160+
#define MCS_6 (6 << 0)
161+
162+
// BBC_OFDMC
163+
#define SSRX 0xC0
164+
#define SSRX_0 (0 << 6)
165+
#define SSRX_1 (1 << 6)
166+
#define SSRX_2 (2 << 6)
167+
#define SSRX_3 (3 << 6)
168+
#define SSTX 0x30
169+
#define SSTX_0 (0 << 4)
170+
#define SSTX_1 (1 << 4)
171+
#define SSTX_2 (2 << 4)
172+
#define SSTX_3 (3 << 4)
173+
#define LFO (1 << 3)
174+
#define POI (1 << 2)
175+
#define OPT 0x03
176+
#define OPT_1 (0 << 0)
177+
#define OPT_2 (1 << 0)
178+
#define OPT_3 (2 << 0)
179+
#define OPT_4 (3 << 0)
180+
181+
// BBC_OFDMSW
182+
#define OFDM_PDT 0xE0
183+
#define OFDM_PDT_5 (5 << 5)
184+
#define OFDM_PDT_4 (4 << 5)
185+
#define OFDM_PDT_3 (3 << 5)
186+
147187
// BBC_FSKC0
148188
#define BT 0xC0
149189
#define BT_20 (3 << 6)

‎components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp‎

Lines changed: 129 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,7 @@ static int rf_set_channel(uint16_t channel, rf_modules_e module);
9999
static int rf_set_ch0_frequency(uint32_t frequency, rf_modules_e module);
100100
static int rf_set_channel_spacing(uint32_t channel_spacing, rf_modules_e module);
101101
static int rf_set_fsk_symbol_rate_configuration(uint32_t symbol_rate, rf_modules_e module);
102+
static int rf_configure_by_ofdm_bandwidth_option(uint8_t option, uint32_t data_rate, rf_modules_e module);
102103
static void rf_calculate_symbol_rate(uint32_t baudrate, phy_modulation_e modulation);
103104
static void rf_conf_set_cca_threshold(uint8_t percent);
104105
// Defined register read/write functions
@@ -300,6 +301,9 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
300301
case PHY_EXTENSION_SET_CCA_THRESHOLD:
301302
rf_conf_set_cca_threshold(*data_ptr);
302303
break;
304+
case PHY_EXTENSION_SET_CHANNEL_CCA_THRESHOLD:
305+
cca_threshold = (int8_t) *data_ptr; // *NOPAD*
306+
break;
303307
case PHY_EXTENSION_SET_802_15_4_MODE:
304308
mac_mode = (phy_802_15_4_mode_t) *data_ptr; // *NOPAD*
305309
if (mac_mode == IEEE_802_15_4_2011) {
@@ -378,7 +382,8 @@ static void rf_init(void)
378382
static void rf_init_registers(rf_modules_e module)
379383
{
380384
// O-QPSK configuration using IEEE Std 802.15.4-2011
381-
// FSK configuration using IEEE Std 802.15.4g-2012
385+
// FSK/OFDM configuration using IEEE Std 802.15.4g-2012
386+
// OFDM configuration is experimental only
382387
if (mac_mode == IEEE_802_15_4_2011) {
383388
device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE;
384389
// 16-bit FCS
@@ -405,40 +410,59 @@ static void rf_init_registers(rf_modules_e module)
405410
rf_write_bbc_register_field(BBC_AFFTM, module, TYPE_2, TYPE_2);
406411
} else if (mac_mode == IEEE_802_15_4G_2012) {
407412
device_driver.link_type = PHY_LINK_15_4_SUBGHZ_TYPE;
408-
// Enable FSK
409-
rf_write_bbc_register_field(BBC_PC, module, PT, BB_MRFSK);
410413
// Disable auto ack
411414
rf_write_bbc_register_field(BBC_AMCS, module, AACK, 0);
412415
// Disable address filter unit 0
413416
rf_write_bbc_register_field(BBC_AFC0, module, AFEN0, 0);
414-
// Set bandwidth time product
415-
rf_write_bbc_register_field(BBC_FSKC0, module, BT, BT_20);
416-
// Disable interleaving
417-
rf_write_bbc_register_field(BBC_FSKC2, module, FECIE, 0);
418-
// Disable receiver override
419-
rf_write_bbc_register_field(BBC_FSKC2, module, RXO, RXO_DIS);
420-
// Set modulation index
421-
if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) {
422-
rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_05);
423-
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_0);
424-
} else {
425-
rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_10);
426-
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4);
427-
}
428-
// Set Gain control settings
429-
rf_write_rf_register_field(RF_AGCC, module, AVGS, AVGS_8_SAMPLES);
430-
rf_write_rf_register_field(RF_AGCS, module, TGT, TGT_1);
431-
// Set symbol rate and related configurations
432-
rf_set_fsk_symbol_rate_configuration(phy_current_config.datarate, module);
433-
// Set preamble length
434-
uint8_t preamble_len = 24;
435-
if (phy_current_config.datarate < 150000) {
436-
preamble_len = 8;
437-
} else if (phy_current_config.datarate < 300000) {
438-
preamble_len = 12;
417+
// Enable FSK
418+
if (phy_current_config.modulation == M_2FSK) {
419+
rf_write_bbc_register_field(BBC_PC, module, PT, BB_MRFSK);
420+
// Set bandwidth time product
421+
rf_write_bbc_register_field(BBC_FSKC0, module, BT, BT_20);
422+
// Disable interleaving
423+
rf_write_bbc_register_field(BBC_FSKC2, module, FECIE, 0);
424+
// Disable receiver override
425+
rf_write_bbc_register_field(BBC_FSKC2, module, RXO, RXO_DIS);
426+
// Set modulation index
427+
if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) {
428+
rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_05);
429+
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_0);
430+
} else {
431+
rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_10);
432+
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4);
433+
}
434+
// Set Gain control settings
435+
rf_write_rf_register_field(RF_AGCC, module, AVGS, AVGS_8_SAMPLES);
436+
rf_write_rf_register_field(RF_AGCS, module, TGT, TGT_1);
437+
// Set symbol rate and related configurations
438+
rf_set_fsk_symbol_rate_configuration(phy_current_config.datarate, module);
439+
// Set preamble length
440+
uint8_t preamble_len = 24;
441+
if (phy_current_config.datarate < 150000) {
442+
preamble_len = 8;
443+
} else if (phy_current_config.datarate < 300000) {
444+
preamble_len = 12;
445+
}
446+
rf_write_bbc_register(BBC_FSKPLL, module, preamble_len);
447+
// Set preamble detector threshold
448+
rf_write_bbc_register_field(BBC_FSKC3, module, PDT, PDT_6);
449+
} else if (phy_current_config.modulation == M_OFDM) {
450+
rf_write_bbc_register_field(BBC_PC, module, PT, BB_MROFDM);
451+
// Set TX scrambler seed
452+
rf_write_bbc_register_field(BBC_OFDMC, module, SSTX, SSTX_0);
453+
// Set RX scrambler seed
454+
rf_write_bbc_register_field(BBC_OFDMC, module, SSRX, SSRX_0);
455+
// Set phyOFDMInterleaving
456+
rf_write_bbc_register_field(BBC_OFDMC, module, POI, 0);
457+
// Set low frequency offset bit
458+
rf_write_bbc_register_field(BBC_OFDMC, module, LFO, 0);
459+
// Configure using bandwidth option
460+
rf_configure_by_ofdm_bandwidth_option(4, 300000, module);
461+
// Set Gain control settings
462+
rf_write_rf_register_field(RF_AGCC, module, AVGS, AVGS_8_SAMPLES);
463+
rf_write_rf_register_field(RF_AGCC, module, AGCI, 0);
464+
rf_write_rf_register_field(RF_AGCS, module, TGT, TGT_3);
439465
}
440-
rf_write_bbc_register(BBC_FSKPLL, module, preamble_len);
441-
rf_write_bbc_register_field(BBC_FSKC3, module, PDT, PDT_6);
442466
}
443467
// Disable filtering FCS
444468
rf_write_bbc_register_field(BBC_PC, module, FCSFE, 0);
@@ -488,9 +512,10 @@ static int8_t rf_start_csma_ca(uint8_t *data_ptr, uint16_t data_length, uint8_t
488512
tx_sequence = *(data_ptr + 2);
489513
}
490514
rf_write_tx_buffer(data_ptr, data_length, rf_module);
491-
if (phy_current_config.modulation == M_OQPSK) {
515+
// Add CRC bytes
516+
if (mac_mode == IEEE_802_15_4_2011) {
492517
data_length += 2;
493-
} else if (phy_current_config.modulation == M_2FSK) {
518+
} else {
494519
data_length += 4;
495520
}
496521
rf_write_tx_packet_length(data_length, rf_module);
@@ -614,9 +639,10 @@ static void rf_handle_rx_done(void)
614639
rf_handle_ack(rx_buffer[2], rx_buffer[0] & MAC_DATA_PENDING);
615640
} else {
616641
int8_t rssi = (int8_t) rf_read_rf_register(RF_EDV, rf_module);
617-
if (phy_current_config.modulation == M_OQPSK) {
642+
// Cut CRC bytes
643+
if (mac_mode == IEEE_802_15_4_2011) {
618644
cur_rx_packet_len -= 2;
619-
} else if (phy_current_config.modulation == M_2FSK) {
645+
} else {
620646
cur_rx_packet_len -= 4;
621647
}
622648
device_driver.phy_rx_cb(rx_buffer, cur_rx_packet_len, 0xf0, rssi, rf_radio_driver_id);
@@ -1055,6 +1081,75 @@ static int rf_set_fsk_symbol_rate_configuration(uint32_t symbol_rate, rf_modules
10551081
return 0;
10561082
}
10571083

1084+
static int rf_configure_by_ofdm_bandwidth_option(uint8_t option, uint32_t data_rate, rf_modules_e module)
1085+
{
1086+
if (!option || option > 4) {
1087+
return -1;
1088+
}
1089+
uint32_t datarate_tmp = 100000 >> (option - 1);
1090+
1091+
// Set modulation and coding scheme
1092+
if (data_rate == datarate_tmp) {
1093+
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_0);
1094+
} else if (data_rate == datarate_tmp * 2) {
1095+
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_1);
1096+
} else if (data_rate == datarate_tmp * 4) {
1097+
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_2);
1098+
} else if (data_rate == datarate_tmp * 8) {
1099+
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_3);
1100+
} else if (data_rate == datarate_tmp * 12) {
1101+
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_4);
1102+
} else if (data_rate == datarate_tmp * 16) {
1103+
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_5);
1104+
} else if (data_rate == datarate_tmp * 24) {
1105+
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_6);
1106+
} else {
1107+
return -1;
1108+
}
1109+
if (option == 1) {
1110+
rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_1);
1111+
rf_write_rf_register_field(RF_TXDFE, module, SR, SR_3);
1112+
rf_write_rf_register_field(RF_RXDFE, module, SR, SR_3);
1113+
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4);
1114+
rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_4);
1115+
rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC800KHZ);
1116+
rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW1250KHZ_IF2000KHZ);
1117+
rf_write_rf_register_field(RF_RXBWC, module, IFS, IFS);
1118+
rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_5);
1119+
} else if (option == 2) {
1120+
rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_2);
1121+
rf_write_rf_register_field(RF_TXDFE, module, SR, SR_3);
1122+
rf_write_rf_register_field(RF_RXDFE, module, SR, SR_3);
1123+
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_3);
1124+
rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_2);
1125+
rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC500KHZ);
1126+
rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW800KHZ_IF1000KHZ);
1127+
rf_write_rf_register_field(RF_RXBWC, module, IFS, IFS);
1128+
rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_5);
1129+
} else if (option == 3) {
1130+
rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_3);
1131+
rf_write_rf_register_field(RF_TXDFE, module, SR, SR_6);
1132+
rf_write_rf_register_field(RF_RXDFE, module, SR, SR_6);
1133+
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_3);
1134+
rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_2);
1135+
rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC250KHZ);
1136+
rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW400KHZ_IF500KHZ);
1137+
rf_write_rf_register_field(RF_RXBWC, module, IFS, 0);
1138+
rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_4);
1139+
} else if (option == 4) {
1140+
rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_4);
1141+
rf_write_rf_register_field(RF_TXDFE, module, SR, SR_6);
1142+
rf_write_rf_register_field(RF_RXDFE, module, SR, SR_6);
1143+
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_2);
1144+
rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_1);
1145+
rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC160KHZ);
1146+
rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW250KHZ_IF250KHZ);
1147+
rf_write_rf_register_field(RF_RXBWC, module, IFS, 1);
1148+
rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_3);
1149+
}
1150+
return 0;
1151+
}
1152+
10581153
static void rf_conf_set_cca_threshold(uint8_t percent)
10591154
{
10601155
uint8_t step = (MAX_CCA_THRESHOLD - MIN_CCA_THRESHOLD);

‎components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/*!
22
* Copyright (c) 2015, Freescale Semiconductor, Inc.
33
* All rights reserved.
4+
* SPDX-License-Identifier: BSD-3-Clause
45
*
56
* \file MCR20Drv.c
67
*
@@ -114,9 +115,7 @@ void MCR20Drv_Init
114115
xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
115116

116117
gXcvrDeassertCS_d();
117-
#if !defined(TARGET_KW24D)
118118
MCR20Drv_RST_B_Deassert();
119-
#endif
120119
RF_IRQ_Init();
121120
RF_IRQ_Disable();
122121
mPhyIrqDisableCnt = 1;
@@ -639,7 +638,6 @@ void MCR20Drv_RESET
639638
void
640639
)
641640
{
642-
#if !defined(TARGET_KW24D)
643641
volatile uint32_t delay = 1000;
644642
//assert RST_B
645643
MCR20Drv_RST_B_Assert();
@@ -648,7 +646,6 @@ void MCR20Drv_RESET
648646

649647
//deassert RST_B
650648
MCR20Drv_RST_B_Deassert();
651-
#endif
652649
}
653650

654651
/*---------------------------------------------------------------------------

‎components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/*!
22
* Copyright (c) 2015, Freescale Semiconductor, Inc.
33
* All rights reserved.
4+
* SPDX-License-Identifier: BSD-3-Clause
45
*
56
* \file MCR20Drv.h
67
*

‎components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Overwrites.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/*!
22
* Copyright (c) 2015, Freescale Semiconductor, Inc.
33
* All rights reserved.
4+
* SPDX-License-Identifier: BSD-3-Clause
45
*
56
* \file MCR20Overwrites.h
67
* Description: Overwrites header file for MCR20 Register values

‎components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Reg.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/*!
22
* Copyright (c) 2015, Freescale Semiconductor, Inc.
33
* All rights reserved.
4+
* SPDX-License-Identifier: BSD-3-Clause
45
*
56
* \file MCR20reg.h
67
* MCR20 Registers

‎components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -61,11 +61,7 @@ extern "C" {
6161
#define gCcaCCA_MODE1_c 1
6262

6363
#define gXcvrRunState_d gXcvrPwrAutodoze_c
64-
#if !defined(TARGET_KW24D)
6564
#define gXcvrLowPowerState_d gXcvrPwrHibernate_c
66-
#else
67-
#define gXcvrLowPowerState_d gXcvrPwrAutodoze_c
68-
#endif
6965

7066
namespace {
7167

@@ -504,9 +500,7 @@ static void rf_init(void)
504500
/* Disable Tristate on MISO for SPI reads */
505501
MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, 0x02);
506502
/* Set XCVR clock output settings */
507-
#if !defined(TARGET_KW24D)
508503
MCR20Drv_Set_CLK_OUT_Freq(gMCR20_ClkOutFreq_d);
509-
#endif
510504
/* Set default XCVR power state */
511505
rf_set_power_state(gXcvrRunState_d);
512506

@@ -1758,7 +1752,7 @@ void NanostackRfPhyMcr20a::_pins_clear()
17581752
irq_thread = NULL;
17591753
}
17601754

1761-
#if MBED_CONF_MCR20A_PROVIDE_DEFAULT || TARGET_KW24D
1755+
#if MBED_CONF_MCR20A_PROVIDE_DEFAULT
17621756

17631757
NanostackRfPhy &NanostackRfPhy::get_default_instance()
17641758
{

‎components/802.15.4_RF/mcr20a-rf-driver/source/XcvrSpi.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/*!
22
* Copyright (c) 2015, Freescale Semiconductor, Inc.
33
* All rights reserved.
4+
* SPDX-License-Identifier: BSD-3-Clause
45
*
56
* \file XcvrSpi.h
67
*

0 commit comments

Comments
 (0)