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loongson-jvmloongson-jvm
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Update (2023.09.20)
32186: LA port of 8314020: Print instruction blocks in byte units 32187: LA port of 8308340: C2: Idealize Fma nodes
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2 files changed

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‎src/hotspot/cpu/loongarch/loongarch_64.ad‎

Lines changed: 30 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -985,6 +985,12 @@ bool Matcher::match_rule_supported(int opcode) {
985985
case Op_PopCountI:
986986
case Op_PopCountL:
987987
return UsePopCountInstruction;
988+
case Op_FmaF:
989+
case Op_FmaD:
990+
case Op_FmaVF:
991+
case Op_FmaVD:
992+
if (!UseFMA)
993+
return false;
988994
default:
989995
break;
990996
}
@@ -9819,125 +9825,101 @@ instruct sqrtF_reg(regF dst, regF src) %{
98199825

98209826
// src1 * src2 + src3
98219827
instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9822-
predicate(UseFMA);
98239828
match(Set dst (FmaF src3 (Binary src1 src2)));
9824-
98259829
format %{ "fmadd_s $dst, $src1, $src2, $src3" %}
9826-
98279830
ins_encode %{
9831+
assert(UseFMA, "Needs FMA instructions support.");
98289832
__ fmadd_s(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg),
98299833
as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
98309834
%}
9831-
98329835
ins_pipe( fpu_arith3 );
98339836
%}
98349837

98359838
// src1 * src2 + src3
98369839
instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9837-
predicate(UseFMA);
98389840
match(Set dst (FmaD src3 (Binary src1 src2)));
9839-
98409841
format %{ "fmadd_d $dst, $src1, $src2, $src3" %}
9841-
98429842
ins_encode %{
9843+
assert(UseFMA, "Needs FMA instructions support.");
98439844
__ fmadd_d(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg),
98449845
as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
98459846
%}
9846-
98479847
ins_pipe( fpu_arith3 );
98489848
%}
98499849

98509850
// src1 * src2 - src3
98519851
instruct msubF_reg_reg(regF dst, regF src1, regF src2, regF src3, immF_0 zero) %{
9852-
predicate(UseFMA);
98539852
match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
9854-
98559853
format %{ "fmsub_s $dst, $src1, $src2, $src3" %}
9856-
98579854
ins_encode %{
9855+
assert(UseFMA, "Needs FMA instructions support.");
98589856
__ fmsub_s(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg),
98599857
as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
98609858
%}
9861-
98629859
ins_pipe( fpu_arith3 );
98639860
%}
98649861

98659862
// src1 * src2 - src3
98669863
instruct msubD_reg_reg(regD dst, regD src1, regD src2, regD src3, immD_0 zero) %{
9867-
predicate(UseFMA);
98689864
match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
9869-
98709865
format %{ "fmsub_d $dst, $src1, $src2, $src3" %}
9871-
98729866
ins_encode %{
9867+
assert(UseFMA, "Needs FMA instructions support.");
98739868
__ fmsub_d(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg),
98749869
as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
98759870
%}
9876-
98779871
ins_pipe( fpu_arith3 );
98789872
%}
98799873

9880-
// -src1 * src2 - src3
9874+
// src1 * (-src2) - src3
9875+
// "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
98819876
instruct mnaddF_reg_reg(regF dst, regF src1, regF src2, regF src3, immF_0 zero) %{
9882-
predicate(UseFMA);
9883-
match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
98849877
match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
9885-
98869878
format %{ "fnmadds $dst, $src1, $src2, $src3" %}
9887-
98889879
ins_encode %{
9880+
assert(UseFMA, "Needs FMA instructions support.");
98899881
__ fnmadd_s(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg),
98909882
as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
98919883
%}
9892-
98939884
ins_pipe( fpu_arith3 );
98949885
%}
98959886

9896-
// -src1 * src2 - src3
9887+
// src1 * (-src2) - src3
9888+
// "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
98979889
instruct mnaddD_reg_reg(regD dst, regD src1, regD src2, regD src3, immD_0 zero) %{
9898-
predicate(UseFMA);
9899-
match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
99009890
match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
9901-
99029891
format %{ "fnmaddd $dst, $src1, $src2, $src3" %}
9903-
99049892
ins_encode %{
9893+
assert(UseFMA, "Needs FMA instructions support.");
99059894
__ fnmadd_d(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg),
99069895
as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
99079896
%}
9908-
99099897
ins_pipe( fpu_arith3 );
99109898
%}
99119899

9912-
// -src1 * src2 + src3
9900+
// src1 * (-src2) + src3
9901+
// "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
99139902
instruct mnsubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9914-
predicate(UseFMA);
9915-
match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
99169903
match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
9917-
99189904
format %{ "fnmsubs $dst, $src1, $src2, $src3" %}
9919-
99209905
ins_encode %{
9906+
assert(UseFMA, "Needs FMA instructions support.");
99219907
__ fnmsub_s(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg),
99229908
as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
99239909
%}
9924-
99259910
ins_pipe( fpu_arith3 );
99269911
%}
99279912

9928-
// -src1 * src2 + src3
9913+
// src1 * (-src2) + src3
9914+
// "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
99299915
instruct mnsubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9930-
predicate(UseFMA);
9931-
match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
99329916
match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
9933-
99349917
format %{ "fnmsubd $dst, $src1, $src2, $src3" %}
9935-
99369918
ins_encode %{
9919+
assert(UseFMA, "Needs FMA instructions support.");
99379920
__ fnmsub_d(as_FloatRegister($dst$$reg), as_FloatRegister($src1$$reg),
99389921
as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
99399922
%}
9940-
99419923
ins_pipe( fpu_arith3 );
99429924
%}
99439925

@@ -13586,6 +13568,7 @@ instruct fmaddV(vReg dst, vReg src1, vReg src2, vReg src3) %{
1358613568
match(Set dst (FmaVD src3 (Binary src1 src2)));
1358713569
format %{ "(x)vfmadd $dst, $src1, $src2, $src3\t# @fmaddV" %}
1358813570
ins_encode %{
13571+
assert(UseFMA, "Needs FMA instructions support.");
1358913572
if (Matcher::vector_length_in_bytes(this) > 16) {
1359013573
switch(Matcher::vector_element_basic_type(this)) {
1359113574
case T_FLOAT : __ xvfmadd_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister); break;
@@ -13642,6 +13625,7 @@ instruct fmsubV(vReg dst, vReg src1, vReg src2, vReg src3) %{
1364213625
match(Set dst (FmaVF (NegVF src3) (Binary src1 src2)));
1364313626
format %{ "(x)vfmsub $dst, $src1, $src2, $src3\t# @fmsubV" %}
1364413627
ins_encode %{
13628+
assert(UseFMA, "Needs FMA instructions support.");
1364513629
if (Matcher::vector_length_in_bytes(this) > 16) {
1364613630
switch(Matcher::vector_element_basic_type(this)) {
1364713631
case T_FLOAT : __ xvfmsub_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister); break;
@@ -13663,14 +13647,14 @@ instruct fmsubV(vReg dst, vReg src1, vReg src2, vReg src3) %{
1366313647

1366413648
// --------------------------------- FNMADD -----------------------------------
1366513649

13666-
// -src1 * src2 - src3
13650+
// src1 * (-src2) - src3
13651+
// "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
1366713652
instruct fnmaddV(vReg dst, vReg src1, vReg src2, vReg src3) %{
13668-
match(Set dst (FmaVF (NegVF src3) (Binary (NegVF src1) src2)));
1366913653
match(Set dst (FmaVF (NegVF src3) (Binary src1 (NegVF src2))));
13670-
match(Set dst (FmaVD (NegVD src3) (Binary (NegVD src1) src2)));
1367113654
match(Set dst (FmaVD (NegVD src3) (Binary src1 (NegVD src2))));
1367213655
format %{ "(x)vfnmadd $dst, $src1, $src2, $src3\t# @fnmaddV" %}
1367313656
ins_encode %{
13657+
assert(UseFMA, "Needs FMA instructions support.");
1367413658
if (Matcher::vector_length_in_bytes(this) > 16) {
1367513659
switch(Matcher::vector_element_basic_type(this)) {
1367613660
case T_FLOAT : __ xvfnmadd_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister); break;
@@ -13692,14 +13676,14 @@ instruct fnmaddV(vReg dst, vReg src1, vReg src2, vReg src3) %{
1369213676

1369313677
// --------------------------------- FNMSUB -----------------------------------
1369413678

13695-
// -src1 * src2 + src3
13679+
// src1 * (-src2) + src3
13680+
// "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
1369613681
instruct fnmsubV(vReg dst, vReg src1, vReg src2, vReg src3) %{
13697-
match(Set dst (FmaVF src3 (Binary (NegVF src1) src2)));
1369813682
match(Set dst (FmaVF src3 (Binary src1 (NegVF src2))));
13699-
match(Set dst (FmaVD src3 (Binary (NegVD src1) src2)));
1370013683
match(Set dst (FmaVD src3 (Binary src1 (NegVD src2))));
1370113684
format %{ "(x)vfnmsub $dst, $src1, $src2, $src3\t# @fnmsubV" %}
1370213685
ins_encode %{
13686+
assert(UseFMA, "Needs FMA instructions support.");
1370313687
if (Matcher::vector_length_in_bytes(this) > 16) {
1370413688
switch(Matcher::vector_element_basic_type(this)) {
1370513689
case T_FLOAT : __ xvfnmsub_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister); break;

‎src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -471,7 +471,7 @@ void os::print_tos_pc(outputStream *st, const void *context) {
471471
// point to garbage if entry point in an nmethod is corrupted. Leave
472472
// this at the end, and hope for the best.
473473
address pc = os::fetch_frame_from_context(uc).pc();
474-
print_instructions(st, pc, 4/*native instruction size*/);
474+
print_instructions(st, pc);
475475
st->cr();
476476
}
477477

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