Update (2023.01.07)

29345: No need to preserve static regs in throw_exception stub frame
28537: forward_exception_entry should not require exception_pc on stack
29399: 8299439: java/text/Format/NumberFormat/CurrencyFormat.java fails for hr_HR
29389: Disable convi2l_type_required
29341: Since T4 can be alloced by C2, it must be saved
29259: Read in the bcp from S0 for the top level interpreter frames
29270: [C2] support {U}DivMod{I/L}
28756: Detach the temp argument of jump_from_interpreted
27559: Corrects the stack offset of SharedRuntime::verify_oop_args()
29266: Delete useless variables and function in class Address
28781: [LA] more configs of Arraycopy stress tests on LA

Author: loongson-jvm

src/hotspot/cpu/loongarch/assembler_loongarch.cpp

@@ -49,31 +49,10 @@
 // Implementation of AddressLiteral
 
 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
-  _is_lval = false;
   _target = target;
   _rspec = rspec_from_rtype(rtype, target);
 }
 
-// Implementation of Address
-
-Address Address::make_array(ArrayAddress adr) {
-  AddressLiteral base = adr.base();
-  Address index = adr.index();
-  assert(index._disp == 0, "must not have disp"); // maybe it can?
-  Address array(index._base, index._index, index._scale, (intptr_t) base.target());
-  array._rspec = base._rspec;
-  return array;
-}
-
-// exceedingly dangerous constructor
-Address::Address(address loc, RelocationHolder spec) {
-  _base  = noreg;
-  _index = noreg;
-  _scale = no_scale;
-  _disp  = (intptr_t) loc;
-  _rspec = spec;
-}
-
 bool Assembler::is_vec_imm(float val) {
   juint x = *reinterpret_cast<juint*>(&val);
   juint masked = x & 0x7e07ffff;

src/hotspot/cpu/loongarch/assembler_loongarch.hpp

@@ -110,9 +110,6 @@ constexpr Register SCR1           = T7;
 // SCR2 is allocable in C2 Compiler
 constexpr Register SCR2           = T4;
 
-
-class ArrayAddress;
-
 class Address {
  public:
   enum ScaleFactor {
@@ -135,12 +132,6 @@ class Address {
   Register         _index;
   ScaleFactor      _scale;
   int              _disp;
-  RelocationHolder _rspec;
-
-  // Easily misused constructors make them private
-  Address(address loc, RelocationHolder spec);
-  Address(int disp, address loc, relocInfo::relocType rtype);
-  Address(int disp, address loc, RelocationHolder spec);
 
  public:
 
@@ -188,8 +179,6 @@ class Address {
   ScaleFactor scale()            const { return _scale; }
   int         disp()             const { return _disp;  }
 
-  static Address make_array(ArrayAddress);
-
   friend class Assembler;
   friend class MacroAssembler;
   friend class LIR_Assembler; // base/index/scale/disp
@@ -205,12 +194,7 @@ class Address {
 // directories.
 //
 class AddressLiteral {
-  friend class ArrayAddress;
   RelocationHolder _rspec;
-  // Typically we use AddressLiterals we want to use their rval
-  // However in some situations we want the lval (effect address) of the item.
-  // We provide a special factory for making those lvals.
-  bool _is_lval;
 
   // If the target is far we'll need to load the ea of this to
   // a register to reach it. Otherwise if near we can do rip
@@ -221,8 +205,7 @@ class AddressLiteral {
  protected:
   // creation
   AddressLiteral()
-    : _is_lval(false),
-      _target(NULL)
+    : _target(NULL)
   {}
 
   public:
@@ -232,21 +215,12 @@ class AddressLiteral {
 
   AddressLiteral(address target, RelocationHolder const& rspec)
     : _rspec(rspec),
-      _is_lval(false),
       _target(target)
   {}
 
-  AddressLiteral addr() {
-    AddressLiteral ret = *this;
-    ret._is_lval = true;
-    return ret;
-  }
-
-
  private:
 
   address target() { return _target; }
-  bool is_lval() { return _is_lval; }
 
   relocInfo::relocType reloc() const { return _rspec.type(); }
   const RelocationHolder& rspec() const { return _rspec; }
@@ -318,25 +292,6 @@ class InternalAddress: public AddressLiteral {
 
 };
 
-// x86 can do array addressing as a single operation since disp can be an absolute
-// address amd64 can't. We create a class that expresses the concept but does extra
-// magic on amd64 to get the final result
-
-class ArrayAddress {
-  private:
-
-  AddressLiteral _base;
-  Address        _index;
-
-  public:
-
-  ArrayAddress() {};
-  ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
-  AddressLiteral base() { return _base; }
-  Address index() { return _index; }
-
-};
-
 // The LoongArch Assembler: Pure assembler doing NO optimizations on the instruction
 // level ; i.e., what you write is what you get. The Assembler is generating code into
 // a CodeBuffer.

src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp

@@ -175,7 +175,7 @@ class InterpreterMacroAssembler: public MacroAssembler {
 
   // jump to an invoked target
   void prepare_to_jump_from_interpreted();
-  void jump_from_interpreted(Register method, Register temp);
+  void jump_from_interpreted(Register method);
 
 
   // Returning from interpreted functions

src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp

@@ -483,29 +483,30 @@ void InterpreterMacroAssembler::store_ptr(int n, Register val) {
   st_d(val, SP, Interpreter::expr_offset_in_bytes(n));
 }
 
-// Jump to from_interpreted entry of a call unless single stepping is possible
-// in this thread in which case we must call the i2i entry
-void InterpreterMacroAssembler::jump_from_interpreted(Register method, Register temp) {
-  // record last_sp
+void InterpreterMacroAssembler::prepare_to_jump_from_interpreted() {
+  // set sender sp
   move(Rsender, SP);
+  // record last_sp
   st_d(SP, FP, frame::interpreter_frame_last_sp_offset * wordSize);
+}
 
+// Jump to from_interpreted entry of a call unless single stepping is possible
+// in this thread in which case we must call the i2i entry
+void InterpreterMacroAssembler::jump_from_interpreted(Register method) {
+  prepare_to_jump_from_interpreted();
   if (JvmtiExport::can_post_interpreter_events()) {
     Label run_compiled_code;
     // JVMTI events, such as single-stepping, are implemented partly by avoiding running
     // compiled code in threads for which the event is enabled.  Check here for
     // interp_only_mode if these events CAN be enabled.
-
-    // interp_only is an int, on little endian it is sufficient to test the byte only
-    // Is a cmpl faster?
-    ld_w(AT, TREG, in_bytes(JavaThread::interp_only_mode_offset()));
-    beq(AT, R0, run_compiled_code);
-    ld_d(AT, method, in_bytes(Method::interpreter_entry_offset()));
+    ld_wu(AT, Address(TREG, JavaThread::interp_only_mode_offset()));
+    beqz(AT, run_compiled_code);
+    ld_d(AT, Address(method, Method::interpreter_entry_offset()));
     jr(AT);
     bind(run_compiled_code);
   }
 
-  ld_d(AT, method, in_bytes(Method::from_interpreted_offset()));
+  ld_d(AT, Address(method, Method::from_interpreted_offset()));
   jr(AT);
 }