@@ -5869,67 +5869,62 @@ instruct vroundD(vReg dst, vReg src, immI rmode) %{
58695869
58705870// anytrue
58715871
5872- instruct vtest_anytrue_neon(iRegINoSp dst , vReg src1, vReg src2, vReg tmp, rFlagsReg cr ) %{
5872+ instruct vtest_anytrue_neon(rFlagsReg cr , vReg src1, vReg src2, vReg tmp) %{
58735873 predicate(UseSVE == 0 &&
58745874 static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::ne);
5875- match(Set dst (VectorTest src1 src2 ));
5876- effect(TEMP tmp, KILL cr );
5877- format %{ "vtest_anytrue_neon $dst, $ src1\t# KILL $tmp, cr " %}
5875+ match(Set cr (VectorTest src1 src2));
5876+ effect(TEMP tmp);
5877+ format %{ "vtest_anytrue_neon $src1\t# KILL $tmp" %}
58785878 ins_encode %{
58795879 // No need to use src2.
58805880 uint length_in_bytes = Matcher::vector_length_in_bytes(this, $src1);
58815881 assert(length_in_bytes == 8 || length_in_bytes == 16, "must be");
58825882 __ addv($tmp$$FloatRegister, length_in_bytes == 16 ? __ T16B : __ T8B, $src1$$FloatRegister);
5883- __ umov($dst$$Register, $tmp$$FloatRegister, __ B, 0);
5884- __ cmpw($dst$$Register, zr);
5885- __ csetw($dst$$Register, Assembler::NE);
5883+ __ umov(rscratch1, $tmp$$FloatRegister, __ B, 0);
5884+ __ cmpw(rscratch1, zr);
58865885 %}
58875886 ins_pipe(pipe_slow);
58885887%}
58895888
5890- instruct vtest_anytrue_sve(iRegINoSp dst , pReg src1, pReg src2, rFlagsReg cr ) %{
5889+ instruct vtest_anytrue_sve(rFlagsReg cr , pReg src1, pReg src2) %{
58915890 predicate(UseSVE > 0 &&
58925891 static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::ne);
5893- match(Set dst (VectorTest src1 src2));
5894- effect(KILL cr);
5895- format %{ "vtest_anytrue_sve $dst, $src1\t# KILL cr" %}
5892+ match(Set cr (VectorTest src1 src2));
5893+ format %{ "vtest_anytrue_sve $src1" %}
58965894 ins_encode %{
58975895 // "src2" is not used for sve.
58985896 __ sve_ptest(ptrue, $src1$$PRegister);
5899- __ csetw($dst$$Register, Assembler::NE);
59005897 %}
59015898 ins_pipe(pipe_slow);
59025899%}
59035900
59045901// alltrue
59055902
5906- instruct vtest_alltrue_neon(iRegINoSp dst , vReg src1, vReg src2, vReg tmp, rFlagsReg cr ) %{
5903+ instruct vtest_alltrue_neon(rFlagsReg cr , vReg src1, vReg src2, vReg tmp) %{
59075904 predicate(UseSVE == 0 &&
59085905 static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::overflow);
5909- match(Set dst (VectorTest src1 src2));
5910- effect(TEMP tmp, KILL cr );
5911- format %{ "vtest_alltrue_neon $dst, $ src1\t# KILL $tmp, cr " %}
5906+ match(Set cr (VectorTest src1 src2));
5907+ effect(TEMP tmp);
5908+ format %{ "vtest_alltrue_neon $src1\t# KILL $tmp" %}
59125909 ins_encode %{
59135910 // No need to use src2.
59145911 uint length_in_bytes = Matcher::vector_length_in_bytes(this, $src1);
59155912 assert(length_in_bytes == 8 || length_in_bytes == 16, "must be");
59165913 __ uminv($tmp$$FloatRegister, length_in_bytes == 16 ? __ T16B : __ T8B, $src1$$FloatRegister);
5917- __ umov($dst$$Register, $tmp$$FloatRegister, __ B, 0);
5918- __ cmpw($dst$$Register, 0xff);
5919- __ csetw($dst$$Register, Assembler::EQ);
5914+ __ umov(rscratch1, $tmp$$FloatRegister, __ B, 0);
5915+ __ cmpw(rscratch1, 0xff);
59205916 %}
59215917 ins_pipe(pipe_slow);
59225918%}
59235919
5924- instruct vtest_alltrue_sve(iRegINoSp dst , pReg src1, pReg src2, pReg ptmp, rFlagsReg cr ) %{
5920+ instruct vtest_alltrue_sve(rFlagsReg cr , pReg src1, pReg src2, pReg ptmp) %{
59255921 predicate(UseSVE > 0 &&
59265922 static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::overflow);
5927- match(Set dst (VectorTest src1 src2));
5928- effect(TEMP ptmp, KILL cr );
5929- format %{ "vtest_alltrue_sve $dst, $ src1, $src2\t# KILL $ptmp, cr " %}
5923+ match(Set cr (VectorTest src1 src2));
5924+ effect(TEMP ptmp);
5925+ format %{ "vtest_alltrue_sve $src1, $src2\t# KILL $ptmp" %}
59305926 ins_encode %{
59315927 __ sve_eors($ptmp$$PRegister, ptrue, $src1$$PRegister, $src2$$PRegister);
5932- __ csetw($dst$$Register, Assembler::EQ);
59335928 %}
59345929 ins_pipe(pipe_slow);
59355930%}
0 commit comments