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loongson-jvmloongson-jvm
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Update (2022.11.02)
26770: [Loom] Virtual Threads Running Stub Implementation 28316: [C2] Vitrual thread awared ThreadLocal node 28312: currentThread entry should be vthread awared 28548: Fix misleading-indentation warnings with minimal and core build 28061: Use Deoptimization::UnrollBlock::initial_info to get FP 28314: Misc crash dump improvements 28272: Delete b*_long() 28046: LA port of 8293035: Cleanup MacroAssembler::movoop code patching logic aarch64 riscv 27813: Inline cache buffer stub code size reduction 22999: Undefine SSR and SHIFT_count 28396: [C2] specify priority of register selection within phases of RA 28524: LA port of 8262074: Consolidate the default value of MetaspaceSize 28280: Implement isFinite intrinsic 28101: Implement isInfinite intrinsic
1 parent c525a38 commit 78e7701

36 files changed

+1781
-667
lines changed

‎src/hotspot/cpu/loongarch/assembler_loongarch.hpp‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -97,14 +97,11 @@ constexpr Register TREG = S6;
9797
constexpr Register S5_heapbase = S5;
9898

9999
constexpr Register FSR = V0;
100-
constexpr Register SSR = T6;
101100
constexpr FloatRegister FSF = FA0;
102101

103102
constexpr Register RECEIVER = T0;
104103
constexpr Register IC_Klass = T1;
105104

106-
constexpr Register SHIFT_count = T3;
107-
108105
// ---------- Scratch Register ----------
109106
constexpr Register AT = T7;
110107
constexpr FloatRegister fscratch = F23;
@@ -1534,27 +1531,18 @@ class Assembler : public AbstractAssembler {
15341531
// get the offset field of beq, bne, blt[u], bge[u] instruction
15351532
int offset16(address entry) {
15361533
assert(is_simm16((entry - pc()) / 4), "change this code");
1537-
if (!is_simm16((entry - pc()) / 4)) {
1538-
tty->print_cr("!!! is_simm16: %lx", (entry - pc()) / 4);
1539-
}
15401534
return (entry - pc()) / 4;
15411535
}
15421536

15431537
// get the offset field of beqz, bnez instruction
15441538
int offset21(address entry) {
15451539
assert(is_simm((int)(entry - pc()) / 4, 21), "change this code");
1546-
if (!is_simm((int)(entry - pc()) / 4, 21)) {
1547-
tty->print_cr("!!! is_simm21: %lx", (entry - pc()) / 4);
1548-
}
15491540
return (entry - pc()) / 4;
15501541
}
15511542

15521543
// get the offset field of b instruction
15531544
int offset26(address entry) {
15541545
assert(is_simm((int)(entry - pc()) / 4, 26), "change this code");
1555-
if (!is_simm((int)(entry - pc()) / 4, 26)) {
1556-
tty->print_cr("!!! is_simm26: %lx", (entry - pc()) / 4);
1557-
}
15581546
return (entry - pc()) / 4;
15591547
}
15601548

‎src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -297,10 +297,7 @@ void LIR_Assembler::jobject2reg(jobject o, Register reg) {
297297
if (o == NULL) {
298298
__ move(reg, R0);
299299
} else {
300-
int oop_index = __ oop_recorder()->find_index(o);
301-
RelocationHolder rspec = oop_Relocation::spec(oop_index);
302-
__ relocate(rspec);
303-
__ patchable_li52(reg, (long)o);
300+
__ movoop(reg, o);
304301
}
305302
}
306303

@@ -2312,6 +2309,7 @@ void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
23122309
return;
23132310
}
23142311
add_call_info(code_offset(), op->info());
2312+
__ post_call_nop();
23152313
}
23162314

23172315
void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
@@ -2321,6 +2319,7 @@ void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
23212319
return;
23222320
}
23232321
add_call_info(code_offset(), op->info());
2322+
__ post_call_nop();
23242323
}
23252324

23262325
void LIR_Assembler::emit_static_call_stub() {
@@ -3166,6 +3165,7 @@ void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* arg
31663165
if (info != NULL) {
31673166
add_call_info_here(info);
31683167
}
3168+
__ post_call_nop();
31693169
}
31703170

31713171
void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type,

‎src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp‎

Lines changed: 15 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -203,68 +203,6 @@ void C2_MacroAssembler::fast_unlock(Register oop, Register box, Register flag,
203203
bind(no_count);
204204
}
205205

206-
void C2_MacroAssembler::beq_long(Register rs, Register rt, Label& L) {
207-
Label not_taken;
208-
209-
bne(rs, rt, not_taken);
210-
211-
jmp_far(L);
212-
213-
bind(not_taken);
214-
}
215-
216-
void C2_MacroAssembler::bne_long(Register rs, Register rt, Label& L) {
217-
Label not_taken;
218-
219-
beq(rs, rt, not_taken);
220-
221-
jmp_far(L);
222-
223-
bind(not_taken);
224-
}
225-
226-
void C2_MacroAssembler::blt_long(Register rs, Register rt, Label& L, bool is_signed) {
227-
Label not_taken;
228-
if (is_signed) {
229-
bge(rs, rt, not_taken);
230-
} else {
231-
bgeu(rs, rt, not_taken);
232-
}
233-
jmp_far(L);
234-
bind(not_taken);
235-
}
236-
237-
void C2_MacroAssembler::bge_long(Register rs, Register rt, Label& L, bool is_signed) {
238-
Label not_taken;
239-
if (is_signed) {
240-
blt(rs, rt, not_taken);
241-
} else {
242-
bltu(rs, rt, not_taken);
243-
}
244-
jmp_far(L);
245-
bind(not_taken);
246-
}
247-
248-
void C2_MacroAssembler::bc1t_long(Label& L) {
249-
Label not_taken;
250-
251-
bceqz(FCC0, not_taken);
252-
253-
jmp_far(L);
254-
255-
bind(not_taken);
256-
}
257-
258-
void C2_MacroAssembler::bc1f_long(Label& L) {
259-
Label not_taken;
260-
261-
bcnez(FCC0, not_taken);
262-
263-
jmp_far(L);
264-
265-
bind(not_taken);
266-
}
267-
268206
typedef void (MacroAssembler::* load_chr_insn)(Register rd, const Address &adr);
269207

270208
void C2_MacroAssembler::string_indexof(Register haystack, Register needle,
@@ -1673,40 +1611,45 @@ void C2_MacroAssembler::cmp_branch_short(int flag, Register op1, Register op2, L
16731611
}
16741612

16751613
void C2_MacroAssembler::cmp_branch_long(int flag, Register op1, Register op2, Label* L, bool is_signed) {
1614+
Label not_taken;
1615+
16761616
switch(flag) {
16771617
case 0x01: //equal
1678-
beq_long(op1, op2, *L);
1618+
bne(op1, op2, not_taken);
16791619
break;
16801620
case 0x02: //not_equal
1681-
bne_long(op1, op2, *L);
1621+
beq(op1, op2, not_taken);
16821622
break;
16831623
case 0x03: //above
16841624
if (is_signed)
1685-
blt_long(op2, op1, *L, true /* signed */);
1625+
bge(op2, op1, not_taken);
16861626
else
1687-
blt_long(op2, op1, *L, false);
1627+
bgeu(op2, op1, not_taken);
16881628
break;
16891629
case 0x04: //above_equal
16901630
if (is_signed)
1691-
bge_long(op1, op2, *L, true /* signed */);
1631+
blt(op1, op2, not_taken);
16921632
else
1693-
bge_long(op1, op2, *L, false);
1633+
bltu(op1, op2, not_taken);
16941634
break;
16951635
case 0x05: //below
16961636
if (is_signed)
1697-
blt_long(op1, op2, *L, true /* signed */);
1637+
bge(op1, op2, not_taken);
16981638
else
1699-
blt_long(op1, op2, *L, false);
1639+
bgeu(op1, op2, not_taken);
17001640
break;
17011641
case 0x06: //below_equal
17021642
if (is_signed)
1703-
bge_long(op2, op1, *L, true /* signed */);
1643+
blt(op2, op1, not_taken);
17041644
else
1705-
bge_long(op2, op1, *L, false);
1645+
bltu(op2, op1, not_taken);
17061646
break;
17071647
default:
17081648
Unimplemented();
17091649
}
1650+
1651+
jmp_far(*L);
1652+
bind(not_taken);
17101653
}
17111654

17121655
void C2_MacroAssembler::cmp_branchEqNe_off21(int flag, Register op1, Label& L) {

‎src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -41,14 +41,6 @@
4141
void fast_unlock(Register oop, Register box, Register flag,
4242
Register disp_hdr, Register tmp);
4343

44-
// For C2 to support long branches
45-
void beq_long (Register rs, Register rt, Label& L);
46-
void bne_long (Register rs, Register rt, Label& L);
47-
void blt_long (Register rs, Register rt, Label& L, bool is_signed);
48-
void bge_long (Register rs, Register rt, Label& L, bool is_signed);
49-
void bc1t_long (Label& L);
50-
void bc1f_long (Label& L);
51-
5244
// Compare strings.
5345
void string_compare(Register str1, Register str2,
5446
Register cnt1, Register cnt2, Register result,

‎src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -79,9 +79,6 @@ define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K);
7979

8080
define_pd_global(bool, TrapBasedRangeChecks, false);
8181

82-
// Heap related flags
83-
define_pd_global(uintx,MetaspaceSize, ScaleForWordSize(16*M));
84-
8582
// Ergonomics related flags
8683
define_pd_global(bool, NeverActAsServerClassMachine, false);
8784

‎src/hotspot/cpu/loongarch/continuationEntry_loongarch.inline.hpp‎

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -28,20 +28,25 @@
2828

2929
#include "runtime/continuationEntry.hpp"
3030

31-
// TODO: Implement
31+
#include "code/codeCache.hpp"
32+
#include "oops/method.inline.hpp"
33+
#include "runtime/frame.inline.hpp"
34+
#include "runtime/registerMap.hpp"
3235

3336
inline frame ContinuationEntry::to_frame() const {
34-
Unimplemented();
35-
return frame();
37+
static CodeBlob* cb = CodeCache::find_blob_fast(entry_pc());
38+
assert(cb != nullptr, "");
39+
assert(cb->as_compiled_method()->method()->is_continuation_enter_intrinsic(), "");
40+
return frame(entry_sp(), entry_sp(), entry_fp(), entry_pc(), cb);
3641
}
3742

3843
inline intptr_t* ContinuationEntry::entry_fp() const {
39-
Unimplemented();
40-
return nullptr;
44+
return (intptr_t*)((address)this + size()) + 2;
4145
}
4246

4347
inline void ContinuationEntry::update_register_map(RegisterMap* map) const {
44-
Unimplemented();
48+
intptr_t** fp = (intptr_t**)(bottom_sender_sp() - 2);
49+
frame::update_map_with_saved_link(map, fp);
4550
}
4651

4752
#endif // CPU_LOONGARCH_CONTINUATIONENTRY_LOONGARCH_INLINE_HPP

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