Update (2023.12.27)

33161: LA port of 8320368: Per-CPU optimization of Klass range reservation
33160: LA port of 8261837: SIGSEGV in ciVirtualCallTypeData::translate_from
33159: LA port of 8318776: Require supports_cx8 to always be true

Author: loongson-jvm

src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp

@@ -1507,7 +1507,6 @@ void LIR_Assembler::casl(Register addr, Register newval, Register cmpval, Regist
 }
 
 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
-  assert(VM_Version::supports_cx8(), "wrong machine");
   Register addr;
   if (op->addr()->is_register()) {
     addr = as_reg(op->addr());
@@ -2977,7 +2976,10 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
   __ verify_oop(obj);
 
   if (tmp != obj) {
+    assert_different_registers(obj, tmp, SCR1, SCR2, mdo_addr.base(), mdo_addr.index());
     __ move(tmp, obj);
+  } else {
+    assert_different_registers(obj, SCR1, SCR2, mdo_addr.base(), mdo_addr.index());
   }
   if (do_null) {
     __ bnez(tmp, update);
@@ -3036,10 +3038,11 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
           __ beqz(SCR2, none);
           __ li(SCR1, (u1)TypeEntries::null_seen);
           __ beq(SCR2, SCR1, none);
-          // There is a chance that the checks above (re-reading profiling
-          // data from memory) fail if another thread has just set the
+          // There is a chance that the checks above
+          // fail if another thread has just set the
           // profiling to this obj's klass
           membar_acquire();
+          __ XOR(tmp, tmp, SCR2); // get back original value before XOR
           __ ld_d(SCR2, mdo_addr);
           __ XOR(tmp, tmp, SCR2);
           assert(TypeEntries::type_klass_mask == -4, "must be");
@@ -3066,6 +3069,11 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
         __ bind(none);
         // first time here. Set profile type.
         __ st_d(tmp, mdo_addr);
+#ifdef ASSERT
+        assert(TypeEntries::type_mask == -2, "must be");
+        __ bstrpick_d(tmp, tmp, 63, 1);
+        __ verify_klass_ptr(tmp);
+#endif
       }
     } else {
       // There's a single possible klass at this profile point
@@ -3099,6 +3107,11 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
 #endif
         // first time here. Set profile type.
         __ st_d(tmp, mdo_addr);
+#ifdef ASSERT
+        assert(TypeEntries::type_mask == -2, "must be");
+        __ bstrpick_d(tmp, tmp, 63, 1);
+        __ verify_klass_ptr(tmp);
+#endif
       } else {
         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");

src/hotspot/cpu/loongarch/compressedKlass_loongarch.cpp

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023, Red Hat, Inc. All rights reserved.
+ * Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2023, Loongson Technology. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#include "precompiled.hpp"
+#include "oops/compressedKlass.hpp"
+#include "utilities/globalDefinitions.hpp"
+
+char* CompressedKlassPointers::reserve_address_space_for_compressed_classes(size_t size, bool aslr, bool optimize_for_zero_base) {
+
+  char* result = nullptr;
+
+  // LoongArch loads a 64-bit immediate in up to four separate steps, splitting it into four different sections
+  // (two 32-bit sections, each split into two subsections of 20/12 bits).
+  //
+  // 63 ....... 52 51 ... 32 31 ....... 12 11 ... 0
+  //       D           C          B           A
+  //
+  // A "good" base is, in this order:
+  // 1) only bits in A; this would be an address < 4KB, which is unrealistic on normal Linux boxes since
+  //    the typical default for vm.mmap_min_address is 64KB. We ignore that.
+  // 2) only bits in B: a 12-bit-aligned address below 4GB. 12 bit = 4KB, but since mmap reserves at
+  //    page boundaries, we can ignore the alignment.
+  // 3) only bits in C: a 4GB-aligned address that is lower than 4PB.
+  // 4) only bits in D: a 4PB-aligned address.
+
+  // First, attempt to allocate < 4GB. We do this unconditionally:
+  // - if can_optimize_for_zero_base, a <4GB mapping start would allow us to run unscaled (base = 0, shift = 0)
+  // - if !can_optimize_for_zero_base, a <4GB mapping start is still good, the resulting immediate can be encoded
+  //   with one instruction (2)
+  result = reserve_address_space_for_unscaled_encoding(size, aslr);
+
+  // Failing that, attempt to reserve for base=zero shift>0
+  if (result == nullptr && optimize_for_zero_base) {
+    result = reserve_address_space_for_zerobased_encoding(size, aslr);
+  }
+
+  // Failing that, optimize for case (3) - a base with only bits set between [33-52)
+  if (result == nullptr) {
+    const uintptr_t from = nth_bit(32 + (optimize_for_zero_base ? LogKlassAlignmentInBytes : 0));
+    constexpr uintptr_t to = nth_bit(52);
+    constexpr size_t alignment = nth_bit(32);
+    result = reserve_address_space_X(from, to, size, alignment, aslr);
+  }
+
+  // Failing that, optimize for case (4) - a base with only bits set between [52-64)
+  if (result == nullptr) {
+    constexpr uintptr_t from = nth_bit(52);
+    constexpr uintptr_t to = UINT64_MAX;
+    constexpr size_t alignment = nth_bit(52);
+    result = reserve_address_space_X(from, to, size, alignment, aslr);
+  }
+
+  return result;
+}

src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp

@@ -1500,6 +1500,7 @@ void InterpreterMacroAssembler::narrow(Register result) {
 
 
 void InterpreterMacroAssembler::profile_obj_type(Register obj, const Address& mdo_addr) {
+  assert_different_registers(obj, AT, T5, mdo_addr.base(), mdo_addr.index());
   Label update, next, none;
 
   verify_oop(obj);
@@ -1538,25 +1539,21 @@ void InterpreterMacroAssembler::profile_obj_type(Register obj, const Address& md
   xorr(obj, obj, AT);
 
   assert(TypeEntries::type_klass_mask == -4, "must be");
-  bstrpick_d(AT, obj, 63, 2);
-  beqz(AT, next);
+  bstrpick_d(T5, obj, 63, 2);
+  beqz(T5, next);
 
-  andi(AT, obj, TypeEntries::type_unknown);
-  bnez(AT, next);
+  andi(T5, obj, TypeEntries::type_unknown);
+  bnez(T5, next);
 
-  if (mdo_addr.index() == noreg) {
-    ld_d(AT, mdo_addr);
-  } else {
-    ld_d(AT, T0, mdo_addr.disp());
-  }
   beqz(AT, none);
 
-  addi_d(AT, AT, -(TypeEntries::null_seen));
-  beqz(AT, none);
+  addi_d(T5, AT, -(TypeEntries::null_seen));
+  beqz(T5, none);
 
-  // There is a chance that the checks above (re-reading profiling
-  // data from memory) fail if another thread has just set the
+  // There is a chance that the checks above
+  // fail if another thread has just set the
   // profiling to this obj's klass
+  xorr(obj, obj, AT); // get back original value before XOR
   if (mdo_addr.index() == noreg) {
     ld_d(AT, mdo_addr);
   } else {
@@ -1588,6 +1585,11 @@ void InterpreterMacroAssembler::profile_obj_type(Register obj, const Address& md
   } else {
     st_d(obj, T0, mdo_addr.disp());
   }
+#ifdef ASSERT
+  assert(TypeEntries::type_mask == -2, "must be");
+  bstrpick_d(obj, obj, 63, 1);
+  verify_klass_ptr(obj);
+#endif
 
   bind(next);
   if (mdo_addr.index() != noreg) {

src/hotspot/cpu/loongarch/loongarch_64.ad

@@ -11823,7 +11823,6 @@ instruct compareAndSwapI(mRegI res, memory_exclusive mem_ptr, mRegI oldval, mReg
 %}
 
 instruct compareAndSwapL(mRegI res, memory_exclusive mem_ptr, mRegL oldval, mRegL newval) %{
-  predicate(VM_Version::supports_cx8());
   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
   effect(TEMP_DEF res);
   ins_cost(3 * MEMORY_REF_COST);

src/hotspot/cpu/loongarch/vm_version_loongarch.cpp

@@ -160,8 +160,6 @@ void VM_Version::get_processor_features() {
   get_cpu_info_stub(&_cpuid_info);
   _features |= get_feature_flags_by_cpucfg();
 
-  _supports_cx8 = true;
-
   if (UseG1GC && FLAG_IS_DEFAULT(MaxGCPauseMillis)) {
     FLAG_SET_DEFAULT(MaxGCPauseMillis, 150);
   }

test/hotspot/jtreg/runtime/CompressedOops/CompressedCPUSpecificClassSpaceReservation.java

@@ -21,6 +21,12 @@
  * questions.
  */
 
+/*
+ * This file has been modified by Loongson Technology in 2023, These
+ * modifications are Copyright (c) 2023 Loongson Technology, and are made
+ * available on the same license terms set forth above.
+ */
+
 /*
  * @test
  * @summary Test the various CPU-specific reservation schemes
@@ -94,6 +100,19 @@ private static void do_test(boolean CDS) throws IOException {
             }
             // bits 44..64
             output.shouldContain("reserve_between (range [0x0000100000000000-0xffffffffffffffff)");
+        } else if (Platform.isLoongArch64()) {
+            output.shouldContain(tryReserveForUnscaled); // unconditionally
+            if (CDS) {
+                output.shouldNotContain(tryReserveForZeroBased);
+                // bits 32..52
+                output.shouldContain("reserve_between (range [0x0000000100000000-0x0010000000000000)");
+            } else {
+                output.shouldContain(tryReserveForZeroBased);
+                // bits 32..52, but not lower than zero-based limit
+                output.shouldContain("reserve_between (range [0x0000000800000000-0x0010000000000000)");
+            }
+            // bits 52..64
+            output.shouldContain("reserve_between (range [0x0010000000000000-0xffffffffffffffff)");
         } else if (Platform.isS390x()) {
             output.shouldContain(tryReserveForUnscaled); // unconditionally
             if (CDS) {