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loongson-jvmloongson-jvm
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Update (2023.08.02, 2nd)
31782: Fix the failure of TestIRMatching.java 31743: LA port of 8312014: [s390x] TestSigInfoInHsErrFile.java Failure 31742: LA port of 8303134: JFR: Missing stack trace during chunk rotation stress 31741: LA port of 8311870: Split CompressedKlassPointers from compressedOops.hpp
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5 files changed

+65
-22
lines changed

5 files changed

+65
-22
lines changed

‎src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
const int BytesPerInstWord = 4;
3030

3131
const int StackAlignmentInBytes = (2*wordSize);
32+
const size_t pd_segfault_address = 1024;
3233

3334
// Indicates whether the C calling conventions require that
3435
// 32-bit integer argument values are properly extended to 64 bits.

‎src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2022, Loongson Technology. All rights reserved.
3+
* Copyright (c) 2022, 2023, Loongson Technology. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -29,6 +29,7 @@
2929
#include "jvmci/jvmciRuntime.hpp"
3030
#include "jvmci/jvmciCompilerToVM.hpp"
3131
#include "jvmci/jvmciJavaClasses.hpp"
32+
#include "oops/compressedKlass.hpp"
3233
#include "oops/oop.inline.hpp"
3334
#include "runtime/handles.inline.hpp"
3435
#include "runtime/jniHandles.hpp"

‎src/hotspot/cpu/loongarch/loongarch_64.ad‎

Lines changed: 10 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1609,7 +1609,7 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bo
16091609
__ st_d(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
16101610
#ifndef PRODUCT
16111611
} else {
1612-
st->print("\tst_d %s, [SP + #%d] # spill 8",
1612+
st->print("\tst_d %s, [SP + #%d]\t# spill 8",
16131613
Matcher::regName[src_first],
16141614
offset);
16151615
#endif
@@ -1659,8 +1659,7 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bo
16591659
__ add_d(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]), R0);
16601660
#ifndef PRODUCT
16611661
} else {
1662-
st->print("\n\t");
1663-
st->print("move(32-bit) %s <-- %s\t# spill 11",
1662+
st->print("\tmove(32-bit) %s <-- %s\t# spill 11",
16641663
Matcher::regName[dst_first],
16651664
Matcher::regName[src_first]);
16661665
#endif
@@ -1677,8 +1676,7 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bo
16771676
__ movgr2fr_d(as_FloatRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
16781677
#ifndef PRODUCT
16791678
} else {
1680-
st->print("\n\t");
1681-
st->print("movgr2fr_d %s, %s\t# spill 12",
1679+
st->print("\tmovgr2fr_d %s, %s\t# spill 12",
16821680
Matcher::regName[dst_first],
16831681
Matcher::regName[src_first]);
16841682
#endif
@@ -1692,8 +1690,7 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bo
16921690
__ movgr2fr_w(as_FloatRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
16931691
#ifndef PRODUCT
16941692
} else {
1695-
st->print("\n\t");
1696-
st->print("movgr2fr_w %s, %s\t# spill 13",
1693+
st->print("\tmovgr2fr_w %s, %s\t# spill 13",
16971694
Matcher::regName[dst_first],
16981695
Matcher::regName[src_first]);
16991696
#endif
@@ -1714,8 +1711,7 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bo
17141711
__ fst_d( as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset) );
17151712
#ifndef PRODUCT
17161713
} else {
1717-
st->print("\n\t");
1718-
st->print("fst_d %s, [SP + #%d]\t# spill 14",
1714+
st->print("\tfst_d %s, [SP + #%d]\t# spill 14",
17191715
Matcher::regName[src_first],
17201716
offset);
17211717
#endif
@@ -1730,8 +1726,7 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bo
17301726
__ fst_s(as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset));
17311727
#ifndef PRODUCT
17321728
} else {
1733-
st->print("\n\t");
1734-
st->print("fst_s %s, [SP + #%d]\t# spill 15",
1729+
st->print("\tfst_s %s, [SP + #%d]\t# spill 15",
17351730
Matcher::regName[src_first],
17361731
offset);
17371732
#endif
@@ -1748,8 +1743,7 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bo
17481743
__ movfr2gr_d( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
17491744
#ifndef PRODUCT
17501745
} else {
1751-
st->print("\n\t");
1752-
st->print("movfr2gr_d %s, %s\t# spill 16",
1746+
st->print("\tmovfr2gr_d %s, %s\t# spill 16",
17531747
Matcher::regName[dst_first],
17541748
Matcher::regName[src_first]);
17551749
#endif
@@ -1763,8 +1757,7 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bo
17631757
__ movfr2gr_s( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
17641758
#ifndef PRODUCT
17651759
} else {
1766-
st->print("\n\t");
1767-
st->print("movfr2gr_s %s, %s\t# spill 17",
1760+
st->print("\tmovfr2gr_s %s, %s\t# spill 17",
17681761
Matcher::regName[dst_first],
17691762
Matcher::regName[src_first]);
17701763
#endif
@@ -1781,8 +1774,7 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bo
17811774
__ fmov_d( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
17821775
#ifndef PRODUCT
17831776
} else {
1784-
st->print("\n\t");
1785-
st->print("fmov_d %s <-- %s\t# spill 18",
1777+
st->print("\tfmov_d %s <-- %s\t# spill 18",
17861778
Matcher::regName[dst_first],
17871779
Matcher::regName[src_first]);
17881780
#endif
@@ -1796,8 +1788,7 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bo
17961788
__ fmov_s( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
17971789
#ifndef PRODUCT
17981790
} else {
1799-
st->print("\n\t");
1800-
st->print("fmov_s %s <-- %s\t# spill 19",
1791+
st->print("\tfmov_s %s <-- %s\t# spill 19",
18011792
Matcher::regName[dst_first],
18021793
Matcher::regName[src_first]);
18031794
#endif

‎src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@
3838
#include "memory/resourceArea.hpp"
3939
#include "memory/universe.hpp"
4040
#include "nativeInst_loongarch.hpp"
41+
#include "oops/compressedKlass.inline.hpp"
4142
#include "oops/compressedOops.inline.hpp"
4243
#include "oops/klass.inline.hpp"
4344
#include "prims/methodHandles.hpp"

‎src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp‎

Lines changed: 51 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5003,6 +5003,47 @@ class StubGenerator: public StubCodeGenerator {
50035003
return stub;
50045004
}
50055005

5006+
// For c2: call to return a leased buffer.
5007+
static RuntimeStub* generate_jfr_return_lease() {
5008+
enum layout {
5009+
fp_off,
5010+
fp_off2,
5011+
return_off,
5012+
return_off2,
5013+
framesize // inclusive of return address
5014+
};
5015+
5016+
int insts_size = 1024;
5017+
int locs_size = 64;
5018+
CodeBuffer code("jfr_return_lease", insts_size, locs_size);
5019+
OopMapSet* oop_maps = new OopMapSet();
5020+
MacroAssembler* masm = new MacroAssembler(&code);
5021+
MacroAssembler* _masm = masm;
5022+
5023+
Label L;
5024+
address start = __ pc();
5025+
__ enter();
5026+
int frame_complete = __ pc() - start;
5027+
address the_pc = __ pc();
5028+
__ bind(L);
5029+
__ set_last_Java_frame(TREG, SP, FP, L);
5030+
__ move(c_rarg0, TREG);
5031+
__ call_VM_leaf(CAST_FROM_FN_PTR(address, JfrIntrinsicSupport::return_lease), 1);
5032+
5033+
__ reset_last_Java_frame(true);
5034+
__ leave();
5035+
__ jr(RA);
5036+
5037+
OopMap* map = new OopMap(framesize, 1);
5038+
oop_maps->add_gc_map(the_pc - start, map);
5039+
5040+
RuntimeStub* stub = // codeBlob framesize is in words (not VMRegImpl::slot_size)
5041+
RuntimeStub::new_runtime_stub("jfr_return_lease", &code, frame_complete,
5042+
(framesize >> (LogBytesPerWord - LogBytesPerInt)),
5043+
oop_maps, false);
5044+
return stub;
5045+
}
5046+
50065047
#endif // INCLUDE_JFR
50075048

50085049
#undef __
@@ -5689,10 +5730,18 @@ class StubGenerator: public StubCodeGenerator {
56895730
StubRoutines::_cont_returnBarrier = generate_cont_returnBarrier();
56905731
StubRoutines::_cont_returnBarrierExc = generate_cont_returnBarrier_exception();
56915732

5692-
JFR_ONLY(StubRoutines::_jfr_write_checkpoint_stub = generate_jfr_write_checkpoint();)
5693-
JFR_ONLY(StubRoutines::_jfr_write_checkpoint = StubRoutines::_jfr_write_checkpoint_stub->entry_point();)
5733+
JFR_ONLY(generate_jfr_stubs();)
56945734
}
56955735

5736+
#if INCLUDE_JFR
5737+
void generate_jfr_stubs() {
5738+
StubRoutines::_jfr_write_checkpoint_stub = generate_jfr_write_checkpoint();
5739+
StubRoutines::_jfr_write_checkpoint = StubRoutines::_jfr_write_checkpoint_stub->entry_point();
5740+
StubRoutines::_jfr_return_lease_stub = generate_jfr_return_lease();
5741+
StubRoutines::_jfr_return_lease = StubRoutines::_jfr_return_lease_stub->entry_point();
5742+
}
5743+
#endif // INCLUDE_JFR
5744+
56965745
void generate_final_stubs() {
56975746
// Generates all stubs and initializes the entry points
56985747

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