Update (2023.08.15)

31942: Implement ExtractV
31838: 32 and 64 bits vector implementation
31751: Use base+disp for cmpxchg
31927: Typo in xBarrierSetAssembler_loongarch.cpp
30985: Insert acqure membar for load-exclusive with acquire
31863: [C2] Effect TEMP_DEF res for cmpxchg

Author: loongson-jvm

src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp

@@ -1511,12 +1511,16 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
 
 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval, Register result, bool sign) {
   __ cmpxchg32(Address(addr, 0), cmpval, newval, result, sign,
-               /* retold */ false, /* barrier */ true, /* weak */ false, /* exchange */ false);
+               /* retold */ false, /* acquire */ true, /* weak */ false, /* exchange */ false);
+  // LA SC equals store-conditional dbar, so no need AnyAny after CAS.
+  //__ membar(__ AnyAny);
 }
 
 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval, Register result) {
   __ cmpxchg(Address(addr, 0), cmpval, newval, result,
-             /* retold */ false, /* barrier */ true, /* weak */ false, /* exchange */ false);
+             /* retold */ false, /* acquire */ true, /* weak */ false, /* exchange */ false);
+  // LA SC equals store-conditional dbar, so no need AnyAny after CAS.
+  //__ membar(__ AnyAny);
 }
 
 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {

src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp

@@ -72,7 +72,7 @@ int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr
     // displaced header address in the object header - if it is not the same, get the
     // object header instead
     lea(SCR2, Address(obj, hdr_offset));
-    cmpxchg(Address(SCR2, 0), hdr, disp_hdr, SCR1, true, false, done);
+    cmpxchg(Address(SCR2, 0), hdr, disp_hdr, SCR1, true, true /* acquire */, done);
     // if the object header was the same, we're done
     // if the object header was not the same, it is now in the hdr register
     // => test if it is a stack pointer into the same stack (recursive locking), i.e.:
@@ -134,9 +134,9 @@ void C1_MacroAssembler::unlock_object(Register hdr, Register obj, Register disp_
     // we do unlocking via runtime call
     if (hdr_offset) {
       lea(SCR1, Address(obj, hdr_offset));
-      cmpxchg(Address(SCR1, 0), disp_hdr, hdr, SCR2, false, false, done, &slow_case);
+      cmpxchg(Address(SCR1, 0), disp_hdr, hdr, SCR2, false, true /* acquire */, done, &slow_case);
     } else {
-      cmpxchg(Address(obj, 0), disp_hdr, hdr, SCR2, false, false, done, &slow_case);
+      cmpxchg(Address(obj, 0), disp_hdr, hdr, SCR2, false, true /* acquire */, done, &slow_case);
     }
     // done
     bind(done);

src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp

@@ -72,7 +72,7 @@ void C2_MacroAssembler::fast_lock_c2(Register oop, Register box, Register flag,
     st_d(tmp, box, BasicLock::displaced_header_offset_in_bytes());
 
     // If cmpxchg is succ, then flag = 1
-    cmpxchg(Address(oop, 0), tmp, box, flag, true, false);
+    cmpxchg(Address(oop, 0), tmp, box, flag, true, true /* acquire */);
     bnez(flag, cont);
 
     // If the compare-and-exchange succeeded, then we found an unlocked
@@ -106,7 +106,7 @@ void C2_MacroAssembler::fast_lock_c2(Register oop, Register box, Register flag,
   // Try to CAS m->owner from null to current thread.
   move(AT, R0);
   addi_d(tmp, disp_hdr, in_bytes(ObjectMonitor::owner_offset()) - markWord::monitor_value);
-  cmpxchg(Address(tmp, 0), AT, TREG, flag, true, false);
+  cmpxchg(Address(tmp, 0), AT, TREG, flag, true, true /* acquire */);
   if (LockingMode != LM_LIGHTWEIGHT) {
     // Store a non-null value into the box to avoid looking like a re-entrant
     // lock. The fast-path monitor unlock code checks for
@@ -166,7 +166,7 @@ void C2_MacroAssembler::fast_unlock_c2(Register oop, Register box, Register flag
     // Check if it is still a light weight lock, this is true if we
     // see the stack address of the basicLock in the markWord of the
     // object.
-    cmpxchg(Address(oop, 0), box, disp_hdr, flag, false, false);
+    cmpxchg(Address(oop, 0), box, disp_hdr, flag, false, false /* acquire */);
     b(cont);
   } else {
     assert(LockingMode == LM_LIGHTWEIGHT, "must be");
@@ -1317,16 +1317,26 @@ void C2_MacroAssembler::reduce(Register dst, Register src, FloatRegister vsrc, F
   } else if (vector_size == 16) {
     vpermi_w(tmp1, vsrc, 0b00001110);
     reduce_ins_v(tmp1, vsrc, tmp1, type, opcode);
+  } else if (vector_size == 8) {
+    vshuf4i_w(tmp1, vsrc, 0b00000001);
+    reduce_ins_v(tmp1, vsrc, tmp1, type, opcode);
+  } else if (vector_size == 4) {
+    vshuf4i_h(tmp1, vsrc, 0b00000001);
+    reduce_ins_v(tmp1, vsrc, tmp1, type, opcode);
   } else {
     ShouldNotReachHere();
   }
 
   if (type != T_LONG) {
-    vshuf4i_w(tmp2, tmp1, 0b00000001);
-    reduce_ins_v(tmp1, tmp2, tmp1, type, opcode);
-    if (type != T_INT) {
-      vshuf4i_h(tmp2, tmp1, 0b00000001);
+    if (vector_size > 8) {
+      vshuf4i_w(tmp2, tmp1, 0b00000001);
       reduce_ins_v(tmp1, tmp2, tmp1, type, opcode);
+    }
+    if (type != T_INT) {
+      if (vector_size > 4) {
+        vshuf4i_h(tmp2, tmp1, 0b00000001);
+        reduce_ins_v(tmp1, tmp2, tmp1, type, opcode);
+      }
       if (type != T_SHORT) {
         vshuf4i_b(tmp2, tmp1, 0b00000001);
         reduce_ins_v(tmp1, tmp2, tmp1, type, opcode);
@@ -1414,6 +1424,11 @@ void C2_MacroAssembler::reduce(FloatRegister dst, FloatRegister src, FloatRegist
       default:
         ShouldNotReachHere();
     }
+  } else if (vector_size == 8) {
+    assert(type == T_FLOAT, "must be");
+    vpermi_w(tmp, vsrc, 0b00000001);
+    reduce_ins_f(dst, vsrc, src, type, opcode);
+    reduce_ins_f(dst, tmp, dst, type, opcode);
   } else {
     ShouldNotReachHere();
   }
@@ -1487,8 +1502,8 @@ void C2_MacroAssembler::vector_compare(FloatRegister dst, FloatRegister src1, Fl
         case BoolTest::eq: xvfcmp_ceq_s (dst, src1, src2); break;
         case BoolTest::ge: xvfcmp_cle_s (dst, src2, src1); break;
         case BoolTest::gt: xvfcmp_clt_s (dst, src2, src1); break;
-        case BoolTest::le: xvfcmp_cule_s(dst, src1, src2); break;
-        case BoolTest::lt: xvfcmp_cult_s(dst, src1, src2); break;
+        case BoolTest::le: xvfcmp_cle_s (dst, src1, src2); break;
+        case BoolTest::lt: xvfcmp_clt_s (dst, src1, src2); break;
         default:
           ShouldNotReachHere();
       }
@@ -1498,15 +1513,15 @@ void C2_MacroAssembler::vector_compare(FloatRegister dst, FloatRegister src1, Fl
         case BoolTest::eq: xvfcmp_ceq_d (dst, src1, src2); break;
         case BoolTest::ge: xvfcmp_cle_d (dst, src2, src1); break;
         case BoolTest::gt: xvfcmp_clt_d (dst, src2, src1); break;
-        case BoolTest::le: xvfcmp_cule_d(dst, src1, src2); break;
-        case BoolTest::lt: xvfcmp_cult_d(dst, src1, src2); break;
+        case BoolTest::le: xvfcmp_cle_d (dst, src1, src2); break;
+        case BoolTest::lt: xvfcmp_clt_d (dst, src1, src2); break;
         default:
           ShouldNotReachHere();
       }
     } else {
       ShouldNotReachHere();
     }
-  } else if (vector_size == 16) {
+  } else if (vector_size == 16 || vector_size == 8 || vector_size == 4) {
     if (bt == T_BYTE) {
       switch (cond) {
         case BoolTest::ne:  vseq_b (dst, src1, src2); vxori_b(dst, dst, 0xff); break;
@@ -1573,8 +1588,8 @@ void C2_MacroAssembler::vector_compare(FloatRegister dst, FloatRegister src1, Fl
         case BoolTest::eq: vfcmp_ceq_s (dst, src1, src2); break;
         case BoolTest::ge: vfcmp_cle_s (dst, src2, src1); break;
         case BoolTest::gt: vfcmp_clt_s (dst, src2, src1); break;
-        case BoolTest::le: vfcmp_cule_s(dst, src1, src2); break;
-        case BoolTest::lt: vfcmp_cult_s(dst, src1, src2); break;
+        case BoolTest::le: vfcmp_cle_s (dst, src1, src2); break;
+        case BoolTest::lt: vfcmp_clt_s (dst, src1, src2); break;
         default:
           ShouldNotReachHere();
       }
@@ -1584,8 +1599,8 @@ void C2_MacroAssembler::vector_compare(FloatRegister dst, FloatRegister src1, Fl
         case BoolTest::eq: vfcmp_ceq_d (dst, src1, src2); break;
         case BoolTest::ge: vfcmp_cle_d (dst, src2, src1); break;
         case BoolTest::gt: vfcmp_clt_d (dst, src2, src1); break;
-        case BoolTest::le: vfcmp_cule_d(dst, src1, src2); break;
-        case BoolTest::lt: vfcmp_cult_d(dst, src1, src2); break;
+        case BoolTest::le: vfcmp_cle_d (dst, src1, src2); break;
+        case BoolTest::lt: vfcmp_clt_d (dst, src1, src2); break;
         default:
           ShouldNotReachHere();
       }

src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp

@@ -463,7 +463,7 @@ void ShenandoahBarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler
 //
 // Clobbers SCR1, SCR2
 void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm,
-                                                Register mem,
+                                                Address addr,
                                                 Register expected,
                                                 Register new_val,
                                                 bool acquire, bool is_cae,
@@ -472,10 +472,9 @@ void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm,
   Register tmp2 = SCR1;
   bool is_narrow = UseCompressedOops;
 
-  assert_different_registers(mem, expected, tmp1, tmp2);
-  assert_different_registers(mem, new_val,  tmp1, tmp2);
+  assert_different_registers(addr.base(), expected, tmp1, tmp2);
+  assert_different_registers(addr.base(), new_val,  tmp1, tmp2);
 
-  Address  addr(mem);
   Label step4, done_succ, done_fail, done;
 
   // There are two ways to reach this label.  Initial entry into the
@@ -513,9 +512,9 @@ void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm,
 
   if (is_narrow) {
     __ cmpxchg32(addr, expected, new_val, tmp2, false /* sign */, false /* retold */,
-                 acquire /* barrier */, false /* weak */, true /* exchange */);
+                 acquire /* acquire */, false /* weak */, true /* exchange */);
   } else {
-    __ cmpxchg(addr, expected, new_val, tmp2, false /* retold */, acquire /* barrier */,
+    __ cmpxchg(addr, expected, new_val, tmp2, false /* retold */, acquire /* acquire */,
                false /* weak */, true /* exchange */);
   }
   // tmp2 holds value fetched.
@@ -579,9 +578,9 @@ void ShenandoahBarrierSetAssembler::cmpxchg_oop(MacroAssembler* masm,
   // compares result with expected.
   if (is_narrow) {
     __ cmpxchg32(addr, tmp2, new_val, tmp1, false /* sign */, false /* retold */,
-                 acquire /* barrier */, false /* weak */, false /* exchange */);
+                 acquire /* acquire */, false /* weak */, false /* exchange */);
   } else {
-    __ cmpxchg(addr, tmp2, new_val, tmp1, false /* retold */, acquire /* barrier */,
+    __ cmpxchg(addr, tmp2, new_val, tmp1, false /* retold */, acquire /* acquire */,
                false /* weak */, false /* exchange */);
   }
   // tmp1 set iff success, tmp2 holds value fetched.

src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.hpp

@@ -81,7 +81,7 @@ class ShenandoahBarrierSetAssembler: public BarrierSetAssembler {
                         Address dst, Register val, Register tmp1, Register tmp2, Register tmp3);
   virtual void try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env,
                                              Register obj, Register tmp, Label& slowpath);
-  void cmpxchg_oop(MacroAssembler* masm, Register mem, Register expected, Register new_val,
+  void cmpxchg_oop(MacroAssembler* masm, Address mem, Register expected, Register new_val,
                    bool acquire, bool is_cae, Register result);
 };