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Commit c87bedf

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Merge branch 'base/hikey' into hikey
2 parents c964e59 + dfe0733 commit c87bedf

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11 files changed

+282
-272
lines changed

11 files changed

+282
-272
lines changed

‎drivers/gpu/drm/hisilicon/hisi_drm_ade.c‎

Lines changed: 76 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727

2828

2929
#define SC_MEDIA_RSTDIS (0x530)
30+
#define SC_MEDIA_RSTEN (0x52C)
3031

3132
enum {
3233
LDI_TEST = 0,
@@ -91,7 +92,6 @@ enum {
9192
ADE_ISR_DMA_ERROR = 0x2000000
9293
};
9394

94-
u8 __iomem *crtc_ade_base;
9595

9696
struct hisi_drm_ade_crtc {
9797

@@ -114,6 +114,7 @@ struct hisi_drm_ade_crtc {
114114

115115
static int hisi_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
116116
struct drm_framebuffer *old_fb);
117+
static void ldi_init(struct hisi_drm_ade_crtc *crtc_ade);
117118

118119
static void ade_init(struct hisi_drm_ade_crtc *crtc_ade)
119120
{
@@ -124,32 +125,31 @@ static void ade_init(struct hisi_drm_ade_crtc *crtc_ade)
124125
cpu0_mask = ADE_ISR_DMA_ERROR;
125126
cpu1_mask = ADE_ISR1_RES_SWITCH_CMPL;
126127

127-
writel(cpu0_mask, (ade_base + INTR_MASK_CPU_0_REG));
128-
writel(cpu1_mask, (ade_base + INTR_MASK_CPU_1_REG));
128+
writel(cpu0_mask, ade_base + INTR_MASK_CPU_0_REG);
129+
writel(cpu1_mask, ade_base + INTR_MASK_CPU_1_REG);
129130
set_TOP_CTL_frm_end_start(ade_base, 2);
130131

131132
/* disable wdma2 and wdma3 frame discard */
132-
writel(0x0, (ade_base + ADE_FRM_DISGARD_CTRL_REG));
133+
writel(0x0, ade_base + ADE_FRM_DISGARD_CTRL_REG);
133134

134-
writel(0, (ade_base + ADE_SOFT_RST_SEL0_REG));
135-
writel(0, (ade_base + ADE_SOFT_RST_SEL1_REG));
136-
writel(0, (ade_base + ADE_RELOAD_DIS0_REG));
137-
writel(0, (ade_base + ADE_RELOAD_DIS1_REG));
135+
writel(0, ade_base + ADE_SOFT_RST_SEL0_REG);
136+
writel(0, ade_base + ADE_SOFT_RST_SEL1_REG);
137+
writel(0, ade_base + ADE_RELOAD_DIS0_REG);
138+
writel(0, ade_base + ADE_RELOAD_DIS1_REG);
138139

139140
/* enable clk gate */
140141
set_TOP_CTL_clk_gate_en(ade_base, 1);
141142

142143
/* init ovly ctrl, if not,when the first
143144
* frame is hybrid, will happen 32112222
144145
*/
145-
writel(0, (ade_base + ADE_OVLY_CTL_REG));
146+
writel(0, ade_base + ADE_OVLY_CTL_REG);
146147

147148
/* TODO:init scl coeff */
148149
}
149150

150-
static int set_hisi_drm_ade_power_clk_enable(struct hisi_drm_ade_crtc *crtc_ade)
151+
static int ade_power_up(struct hisi_drm_ade_crtc *crtc_ade)
151152
{
152-
153153
u8 __iomem *media_base = crtc_ade->media_base;
154154
int ret;
155155

@@ -169,7 +169,7 @@ static int set_hisi_drm_ade_power_clk_enable(struct hisi_drm_ade_crtc *crtc_ade)
169169
return ret;
170170
}
171171

172-
writel(0x20, (media_base + SC_MEDIA_RSTDIS));
172+
writel(0x20, media_base + SC_MEDIA_RSTDIS);
173173

174174
ret = clk_prepare_enable(crtc_ade->ade_core_clk);
175175
if (ret) {
@@ -179,23 +179,46 @@ static int set_hisi_drm_ade_power_clk_enable(struct hisi_drm_ade_crtc *crtc_ade)
179179
return 0;
180180
}
181181

182+
static int ade_power_down(struct hisi_drm_ade_crtc *crtc_ade)
183+
{
184+
u8 __iomem *media_base = crtc_ade->media_base;
185+
186+
clk_disable_unprepare(crtc_ade->ade_core_clk);
187+
writel(0x20, media_base + SC_MEDIA_RSTEN);
188+
clk_disable_unprepare(crtc_ade->media_noc_clk);
189+
return 0;
190+
}
191+
182192
static int hisi_drm_crtc_ade_enable(struct hisi_drm_ade_crtc *crtc_ade)
183193
{
184194
int ret;
185195

186-
ret = set_hisi_drm_ade_power_clk_enable(crtc_ade);
196+
ret = ade_power_up(crtc_ade);
187197
if (ret) {
188198
DRM_ERROR("failed to initialize ade clk\n");
189199
return ret;
190200
}
191201

192202
ade_init(crtc_ade);
193-
203+
ldi_init(crtc_ade);
204+
if (crtc_ade->crtc.primary->fb)
205+
hisi_drm_crtc_mode_set_base(&crtc_ade->crtc, 0, 0, NULL);
194206
return 0;
195207
}
196208

197-
static int hisi_drm_crtc_ade_unable(struct hisi_drm_ade_crtc *crtc_ade)
209+
static int hisi_drm_crtc_ade_disable(struct hisi_drm_ade_crtc *crtc_ade)
198210
{
211+
int ret;
212+
u8 __iomem *ade_base = crtc_ade->ade_base;
213+
214+
set_LDI_CTRL_ldi_en(ade_base, ADE_DISABLE);
215+
/* dsi pixel off */
216+
set_reg(ade_base + LDI_HDMI_DSI_GT_REG, 0x1, 1, 0);
217+
ret = ade_power_down(crtc_ade);
218+
if (ret) {
219+
DRM_ERROR("failed to initialize ade clk\n");
220+
return ret;
221+
}
199222

200223
return 0;
201224
}
@@ -230,7 +253,7 @@ static void ldi_init(struct hisi_drm_ade_crtc *crtc_ade)
230253
set_LDI_HRZ_CTRL1_hsw(ade_base, hsync_len);
231254
set_LDI_VRT_CTRL0(ade_base, vfront_porch, vback_porch);
232255
set_LDI_VRT_CTRL1_vsw(ade_base, vsync_len);
233-
writel(plr_flags, (ade_base + LDI_PLR_CTRL_REG));
256+
writel(plr_flags, ade_base + LDI_PLR_CTRL_REG);
234257
set_LDI_DSP_SIZE_size(ade_base, mode->hdisplay, mode->vdisplay);
235258
ret = clk_set_rate(crtc_ade->ade_pix_clk, mode->clock * 1000);
236259
if (ret) {
@@ -244,14 +267,16 @@ static void ldi_init(struct hisi_drm_ade_crtc *crtc_ade)
244267
set_LDI_WORK_MODE_work_mode(ade_base, LDI_WORK);
245268
set_LDI_WORK_MODE_colorbar_en(ade_base, ADE_DISABLE);
246269
ldi_mask = LDI_ISR_FRAME_END_INT | LDI_ISR_UNDER_FLOW_INT;
247-
writel(ldi_mask, (ade_base + LDI_INT_EN_REG));
270+
writel(ldi_mask, ade_base + LDI_INT_EN_REG);
248271

249272
set_LDI_CTRL_bgr(ade_base, ADE_RGB);
250273
set_LDI_CTRL_bpp(ade_base, ADE_OUT_RGB_888);
251274
set_LDI_CTRL_disp_mode(ade_base, LDI_DISP_MODE_NOT_3D_FBF);
252275
set_LDI_CTRL_corlorbar_width(ade_base, 0x3C);
253-
writel(0xFFFFFFFF, (ade_base + LDI_INT_CLR_REG));
276+
writel(0xFFFFFFFF, ade_base + LDI_INT_CLR_REG);
254277
set_reg(ade_base + LDI_DE_SPACE_LOW_REG, 0x1, 1, 1);
278+
/* dsi pixel on */
279+
set_reg(ade_base + LDI_HDMI_DSI_GT_REG, 0x0, 1, 0);
255280
}
256281

257282
/* -----------------------------------------------------------------------------
@@ -271,7 +296,7 @@ static void hisi_drm_crtc_dpms(struct drm_crtc *crtc, int mode)
271296
if (mode == DRM_MODE_DPMS_ON)
272297
hisi_drm_crtc_ade_enable(crtc_ade);
273298
else
274-
hisi_drm_crtc_ade_unable(crtc_ade);
299+
hisi_drm_crtc_ade_disable(crtc_ade);
275300

276301
crtc_ade->dpms = mode;
277302
DRM_DEBUG_DRIVER("crtc_dpms exit successfully.\n");
@@ -288,7 +313,8 @@ static bool hisi_drm_crtc_mode_fixup(struct drm_crtc *crtc,
288313

289314
static void hisi_drm_crtc_mode_prepare(struct drm_crtc *crtc)
290315
{
291-
hisi_drm_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
316+
DRM_DEBUG_DRIVER(" enter successfully.\n");
317+
DRM_DEBUG_DRIVER(" exit successfully.\n");
292318
}
293319

294320
static int hisi_drm_crtc_mode_set(struct drm_crtc *crtc,
@@ -300,11 +326,7 @@ static int hisi_drm_crtc_mode_set(struct drm_crtc *crtc,
300326
struct hisi_drm_ade_crtc *crtc_ade = to_hisi_crtc(crtc);
301327

302328
DRM_DEBUG_DRIVER("mode_set enter successfully.\n");
303-
304329
crtc_ade->dmode = mode;
305-
306-
ldi_init(crtc_ade);
307-
308330
DRM_DEBUG_DRIVER("mode_set exit successfully.\n");
309331
return 0;
310332
}
@@ -313,7 +335,6 @@ static void hisi_drm_crtc_mode_commit(struct drm_crtc *crtc)
313335
{
314336

315337
DRM_DEBUG_DRIVER("mode_commit enter successfully.\n");
316-
hisi_drm_crtc_mode_set_base(crtc, 0, 0, NULL);
317338
DRM_DEBUG_DRIVER("mode_commit exit successfully.\n");
318339
}
319340

@@ -323,6 +344,7 @@ static int hisi_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
323344
struct hisi_drm_ade_crtc *crtc_ade = to_hisi_crtc(crtc);
324345
struct drm_framebuffer *fb = crtc->primary->fb;
325346
struct drm_gem_cma_object *obj = hisi_drm_fb_get_gem_obj(fb, 0);
347+
struct hisi_drm_fb *hisi_fb = to_hisi_drm_fb(fb);
326348

327349
u8 __iomem *ade_base;
328350
u32 stride;
@@ -334,57 +356,58 @@ static int hisi_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
334356
stride = fb->pitches[0];
335357
offset = y * fb->pitches[0] + x * (fb->bits_per_pixel >> 3);
336358
display_addr = (u32)obj->paddr + offset;
337-
fb_hight = fb->height / HISI_NUM_FRAMEBUFFERS;
359+
fb_hight = hisi_fb->is_fbdev_fb ? fb->height / HISI_NUM_FRAMEBUFFERS
360+
: fb->height;
338361

339362
DRM_DEBUG_DRIVER("enter stride=%d,paddr=0x%x,display_addr=0x%x,%dx%d\n",
340363
stride, (u32)obj->paddr, display_addr,
341364
fb->width, fb_hight);
342365

343366
/* TOP setting */
344-
writel(0, (ade_base + ADE_WDMA2_SRC_CFG_REG));
345-
writel(0, (ade_base + ADE_SCL3_MUX_CFG_REG));
346-
writel(0, (ade_base + ADE_SCL1_MUX_CFG_REG));
347-
writel(0, (ade_base + ADE_ROT_SRC_CFG_REG));
348-
writel(0, (ade_base + ADE_SCL2_SRC_CFG_REG));
349-
writel(0, (ade_base + ADE_SEC_OVLY_SRC_CFG_REG));
350-
writel(0, (ade_base + ADE_WDMA3_SRC_CFG_REG));
351-
writel(0, (ade_base + ADE_OVLY1_TRANS_CFG_REG));
352-
writel(0, (ade_base + ADE_CTRAN5_TRANS_CFG_REG));
353-
writel(0, (ade_base + ADE_OVLY_CTL_REG));
354-
writel(0, (ade_base + ADE_SOFT_RST_SEL0_REG));
355-
writel(0, (ade_base + ADE_SOFT_RST_SEL1_REG));
367+
writel(0, ade_base + ADE_WDMA2_SRC_CFG_REG);
368+
writel(0, ade_base + ADE_SCL3_MUX_CFG_REG);
369+
writel(0, ade_base + ADE_SCL1_MUX_CFG_REG);
370+
writel(0, ade_base + ADE_ROT_SRC_CFG_REG);
371+
writel(0, ade_base + ADE_SCL2_SRC_CFG_REG);
372+
writel(0, ade_base + ADE_SEC_OVLY_SRC_CFG_REG);
373+
writel(0, ade_base + ADE_WDMA3_SRC_CFG_REG);
374+
writel(0, ade_base + ADE_OVLY1_TRANS_CFG_REG);
375+
writel(0, ade_base + ADE_CTRAN5_TRANS_CFG_REG);
376+
writel(0, ade_base + ADE_OVLY_CTL_REG);
377+
writel(0, ade_base + ADE_SOFT_RST_SEL0_REG);
378+
writel(0, ade_base + ADE_SOFT_RST_SEL1_REG);
356379
set_TOP_SOFT_RST_SEL0_disp_rdma(ade_base, 1);
357380
set_TOP_SOFT_RST_SEL0_ctran5(ade_base, 1);
358381
set_TOP_SOFT_RST_SEL0_ctran6(ade_base, 1);
359-
writel(0, (ade_base + ADE_RELOAD_DIS0_REG));
360-
writel(0, (ade_base + ADE_RELOAD_DIS1_REG));
361-
writel(TOP_DISP_CH_SRC_RDMA, (ade_base + ADE_DISP_SRC_CFG_REG));
382+
writel(0, ade_base + ADE_RELOAD_DIS0_REG);
383+
writel(0, ade_base + ADE_RELOAD_DIS1_REG);
384+
writel(TOP_DISP_CH_SRC_RDMA, ade_base + ADE_DISP_SRC_CFG_REG);
362385

363386
/* DISP DMA setting */
364387
if (16 == fb->bits_per_pixel)
365388
writel((ADE_RGB_565 << 16) & 0x1f0000,
366-
(ade_base + RD_CH_DISP_CTRL_REG));
389+
ade_base + RD_CH_DISP_CTRL_REG);
367390
else if (32 == fb->bits_per_pixel)
368391
writel((ADE_ABGR_8888 << 16) & 0x1f0000,
369-
(ade_base + RD_CH_DISP_CTRL_REG));
370-
writel(display_addr, (ade_base + RD_CH_DISP_ADDR_REG));
371-
writel(((fb_hight << 16) | stride), (ade_base + RD_CH_DISP_SIZE_REG));
372-
writel(stride, (ade_base + RD_CH_DISP_STRIDE_REG));
373-
writel(fb_hight * stride, (ade_base + RD_CH_DISP_SPACE_REG));
374-
writel(1, (ade_base + RD_CH_DISP_EN_REG));
392+
ade_base + RD_CH_DISP_CTRL_REG);
393+
writel(display_addr, ade_base + RD_CH_DISP_ADDR_REG);
394+
writel((fb_hight << 16) | stride, ade_base + RD_CH_DISP_SIZE_REG);
395+
writel(stride, ade_base + RD_CH_DISP_STRIDE_REG);
396+
writel(fb_hight * stride, ade_base + RD_CH_DISP_SPACE_REG);
397+
writel(1, ade_base + RD_CH_DISP_EN_REG);
375398

376399
/* ctran5 setting */
377-
writel(1, (ade_base + ADE_CTRAN5_DIS_REG));
400+
writel(1, ade_base + ADE_CTRAN5_DIS_REG);
378401
writel(fb->width * fb_hight - 1,
379-
(ade_base + ADE_CTRAN5_IMAGE_SIZE_REG));
402+
ade_base + ADE_CTRAN5_IMAGE_SIZE_REG);
380403

381404
/* ctran6 setting */
382-
writel(1, (ade_base + ADE_CTRAN6_DIS_REG));
405+
writel(1, ade_base + ADE_CTRAN6_DIS_REG);
383406
writel(fb->width * fb_hight - 1,
384-
(ade_base + ADE_CTRAN6_IMAGE_SIZE_REG));
407+
ade_base + ADE_CTRAN6_IMAGE_SIZE_REG);
385408

386409
/* enable ade and ldi */
387-
writel(ADE_ENABLE, (ade_base + ADE_EN_REG));
410+
writel(ADE_ENABLE, ade_base + ADE_EN_REG);
388411
set_TOP_CTL_frm_end_start(ade_base, 1);
389412
set_LDI_CTRL_ldi_en(ade_base, ADE_ENABLE);
390413

@@ -446,11 +469,6 @@ static int hisi_drm_crtc_create(struct hisi_drm_ade_crtc *crtc_ade)
446469
return 0;
447470
}
448471

449-
u8 __iomem *hisi_drm_get_ade_base(void)
450-
{
451-
return crtc_ade_base;
452-
}
453-
454472
static int hisi_drm_ade_dts_parse(struct platform_device *pdev,
455473
struct hisi_drm_ade_crtc *crtc_ade)
456474
{
@@ -476,8 +494,6 @@ static int hisi_drm_ade_dts_parse(struct platform_device *pdev,
476494
ret = PTR_ERR(crtc_ade->media_base);
477495
}
478496

479-
crtc_ade_base = crtc_ade->ade_base;
480-
481497
crtc_ade->ade_core_clk = devm_clk_get(&pdev->dev, "clk_ade_core");
482498
if (crtc_ade->ade_core_clk == NULL) {
483499
DRM_ERROR("failed to parse the ADE_CORE\n");

‎drivers/gpu/drm/hisilicon/hisi_drm_ade.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@
1313
#ifndef __HISI_DRM_ADE_H__
1414
#define __HISI_DRM_ADE_H__
1515

16-
extern u8 __iomem *hisi_drm_get_ade_base(void);
1716
extern int hisi_drm_ade_init(void);
1817
extern void hisi_drm_ade_exit(void);
1918

‎drivers/gpu/drm/hisilicon/hisi_drm_drv.c‎

Lines changed: 31 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414

1515
#include <drm/drmP.h>
1616
#include <drm/drm_fb_helper.h>
17+
#include <drm/drm_gem_cma_helper.h>
1718

1819
#include "hisi_drm_ade.h"
1920
#include "hisi_drm_dsi.h"
@@ -140,16 +141,42 @@ static const struct file_operations hisi_drm_fops = {
140141
.poll = drm_poll,
141142
.read = drm_read,
142143
.llseek = no_llseek,
144+
.mmap = drm_gem_cma_mmap,
143145
};
144146

147+
static struct dma_buf *hisi_drm_gem_prime_export(struct drm_device *dev,
148+
struct drm_gem_object *obj,
149+
int flags)
150+
{
151+
/* we want to be able to write in mmapped buffer */
152+
flags |= O_RDWR;
153+
return drm_gem_prime_export(dev, obj, flags);
154+
}
155+
145156
static struct drm_driver hisi_drm_driver = {
146-
.driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET
147-
| DRIVER_PRIME,
157+
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME,
148158
.load = hisi_drm_load,
149159
.unload = hisi_drm_unload,
150160
.fops = &hisi_drm_fops,
151161
.set_busid = drm_platform_set_busid,
152-
.name = "hisi-drm",
162+
163+
.gem_free_object = drm_gem_cma_free_object,
164+
.gem_vm_ops = &drm_gem_cma_vm_ops,
165+
.dumb_create = drm_gem_cma_dumb_create,
166+
.dumb_map_offset = drm_gem_cma_dumb_map_offset,
167+
.dumb_destroy = drm_gem_dumb_destroy,
168+
169+
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
170+
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
171+
.gem_prime_export = hisi_drm_gem_prime_export,
172+
.gem_prime_import = drm_gem_prime_import,
173+
.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
174+
.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
175+
.gem_prime_vmap = drm_gem_cma_prime_vmap,
176+
.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
177+
.gem_prime_mmap = drm_gem_cma_prime_mmap,
178+
179+
.name = "hisi",
153180
.desc = "Hisilicon Terminal SoCs DRM Driver",
154181
.date = "20141224",
155182
.major = 1,
@@ -190,6 +217,6 @@ static struct platform_driver hisi_drm_platform_driver = {
190217

191218
module_platform_driver(hisi_drm_platform_driver);
192219

193-
MODULE_AUTHOR("");
220+
MODULE_AUTHOR("Xinliang Liu <z.liuxinliang@huawei.com>");
194221
MODULE_DESCRIPTION("HISI DRM Driver");
195222
MODULE_LICENSE("GPL");

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